Correlation of fabrication process and electrical device parameter variations

Dutton, R.W.; Divekar, D.; Gonzalez, A.G.; Hansen, Stephen; Antoniadis, D.A.

doi:10.1109/jssc.1977.1050913

Cited by 21 publications

(2 citation statements)

References 2 publications

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“…Process modeling.--As semiconductor processing has matured and extremely sophisticated computer technology has been developed, projects have been initiated to establish advanced models of the various processes and to adapt them to computer programs (209)(210)(211). The goal of these various activities is to provide computer programs wl~lch can ptot out dopant and other structural profiles resulting from a sequence o5 high temperature treatments, and ultimately to predict resulting device and circuit characteristics.…”

Section: Miscellaneousmentioning

confidence: 99%

The Evolution of Silicon Semiconductor Technology: 1952–1977

Deal

Early

1979

J. Electrochem. Soc.

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Section: Miscellaneousmentioning

confidence: 99%

The Evolution of Silicon Semiconductor Technology: 1952–1977

Deal

Early

1979

J. Electrochem. Soc.

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“…In general, far fewer orthogonal components are needed to generate the device-model instances when using either a process simulator or principle components because the variations in device parameters are strongly correlated [19], [20]. For example, as will be seen in Section V, when using this method to generate BSIM device models with approximately 60 variable parameters, only 11 principle components were needed.…”

Section: B Generating Design Instancesmentioning

confidence: 99%

Rapid yield estimation as a computer aid for analog circuit design

Mukherjee

Carley

1991

IEEE J. Solid-State Circuits

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A rapid yield estimation methodology that aids the analog circuit designer in making design trade-offs that improve yield is presented. This methodology is based on using hierarchical evaluation of analysis equations, rather than simulation, to predict circuit performance. The new analog rapid yield estimation (ARYE) method has been used to predict the yield of two-stage op amps, and has been incorporated into the Carnegie Mellon University (CMU) analog design system (ACACIA). An example of how ARYE allows analog designers to quickly explore the impact of design changes on yield will be presented. The primary goal of ARYE is to make numerous early predictions of parametric yield economical for the analog circuit designer.

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