Rapid yield estimation as a computer aid for analog circuit design

Mukherjee, Tamal; Carley, L.R.

doi:10.1109/4.75008

Cited by 10 publications

(5 citation statements)

References 20 publications

(17 reference statements)

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“…The result shows that a higher yield was achieved with the proposed method. The computational cost is one that can be overcome with a parallelization of the optimization process [15]. Figure 6 Monte Carlo Simulation for Voltage Offset…”

Section: Discussionmentioning

confidence: 99%

“…However, there are some efforts that have been developed that include parameter variations in the analog circuit synthesis. [15], [16] use post-design yield analysis to change the cost function of the inner circuit optimization. While [17] incorporates mismatch parameter as the cost function, but this is done only for global variations and the mismatch is represented by a simplified model rather than simulationbased estimation.…”

Section: Introductionmentioning

confidence: 99%

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Yield Predictive Model Characterization In Analog Circuit Design

Wilson

Brown

2007

2007 International Symposium on Integrated Circuits

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Abstract-A new technique is presented that produces a characterized yield-predictive model by incorporating yield into the goal function directly. We explore the trade off between performance functions and yield estimation during the design optimization process. Through the integration of yield into the optimization process, the trade off between the performance functions can be better treated that able to produce a higher yield. This concept together with full circuit simulation and global search algorithm provides a robust solution across process corners and parameter variations. Encouraging results have been obtained and an example is presented to demonstrate the technique.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Yield Predictive Model Characterization In Analog Circuit Design

Wilson

Brown

2007

2007 International Symposium on Integrated Circuits

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“…This falls short in that it attempts to use the same variability for all devices in a design, regardless of the degree of matching they exhibit. The second method develops an empirical model for each specific matched device configuration, and uses that model to generate specific parameter information for each matched device [14], [15]. This technique requires explicit model development for each new matching configuration (for example, if three matching devices were used rather than two), and assumes that the only within-die variations which matter are those on matched devices (other devices are modeled with no variation).…”

Section: Introductionmentioning

confidence: 99%

Using multivariate nested distributions to model semiconductor manufacturing processes

Gibson

Poddar²,

May

et al. 1999

IEEE Trans. Semicond. Manufact.

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This paper demonstrates the advantages of modeling semiconductor process variability using a multivariate nested distribution. This distribution allows estimation not only of correlation among various model parameters, but also allows each of those variations to be apportioned among the various stages of the process (i.e., wafer-to-wafer, lot-to-lot, etc.). This permits matched devices to be more accurately simulated, without having to develop customized models for each configuration of matching. The technique also provides focus for process improvement efforts into those areas with the maximum potential reward. Test structures have been designed and fabricated to facilitate extraction of the parameters for the multivariate nested distribution. Using data from a sample of these structures, a process model is built and analyzed. Monte Carlo techniques are then employed using SPICE and a probabilistic process model to predict the performance of a multiplying digital-to-analog converter (MDAC), and the results are compared to measured data from fabricated circuits. Simulations performed using a model built using the multivariate nested approach are shown to provide superior results when compared to simulations using currently accepted multivariate normal models.

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“…This falls short in that it attempts to use the same variability for all devices in a design, regardless of the degree of matching they exhibit. The second method develops an empirical model for each specific matched device configuration, and uses that model to generate specific parameter information for each matched device [32], [33]. This technique requires explicit model development for each new matching configuration (for example, if three matching devices were used rather than two), and assumes that the only within-die variations which matter are those on matched devices (other devices are modeled with no variation).…”

Section: Introductionmentioning

confidence: 99%

Statistically based parametric yield prediction for integrated circuits

Gibson

Poddar

May

et al. 1997

IEEE Trans. Semicond. Manufact.

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This paper presents a novel procedure for predicting integrated circuit parametric performance and yield when provided with sample transistor test results and a circuit schematic. Two enhancements to the existing Monte Carlo simulation procedures are described: 1) a multivariate nested model is used to reproduce random process-induced device variations, rather than the multivariate multinormal model typically used, and 2) the stochastic Monte Carlo method for mapping process variability into a performance distribution is replaced with a deterministic mapping technique. The use of multivariate nested distributions allows estimation not only of correlation between various model parameters, but also allows each of those variations to be apportioned among the various stages of the process (i.e., wafer to wafer, lot to lot, etc.). This allows matched devices to be more accurately simulated, without having to develop customized models for each configuration of matching, and provides focus for process improvement efforts into those areas with the maximum potential reward. The use of deterministic mapping provides simulation results which are repeatable and do not rely on chance to insure that the process parameter space has been evenly explored. A software package which implements the entire procedure has been written in C++.

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Rapid yield estimation as a computer aid for analog circuit design

Cited by 10 publications

References 20 publications

Yield Predictive Model Characterization In Analog Circuit Design

Yield Predictive Model Characterization In Analog Circuit Design

Using multivariate nested distributions to model semiconductor manufacturing processes

Statistically based parametric yield prediction for integrated circuits

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