Correlation between DC and rf degradation due to deep levels in AlGaN/GaN HEMTs

Abstract

We investigate the role of the 0.5 eV traps in determining GaN HEMT degradation by means of DC and rf testing, and 2D numerical simulation. We demonstrate that generation of deep levels, having an activation energy of 0.5 eV, is responsible for the degradation observed during rf aging; we show that the occurrence of trap-induced degradation depends on rf driving conditions. We also show that degradation can be explained by the generation of a damaged region within the AlGaN layer at the gate-drain edge, and that the DC and pulsed device degradation effects have a different dependence on the width and depth of the damaged region

Electroluminescence of hot electrons in AlGaN/GaN high-electron-mobility transistors under radio frequency operation

“…The degradation has been attributed to trap formation due to hot carriers. Generation of traps with 0.5 eV activation energy, both due to DC and RF, has been reported by Chini et al, 4 likewise with more severe degradation observed under RF. However, data also exist that suggest that device degradation may actually be no worse or even less under RF operation, compared to DC stressing as, for example, observed by Caesar et al 5 Hence, it is essential to identify the microscopic processes involved in the conduction and degradation mechanisms of high electron mobility transistors (HEMTs) under DC and RF conditions, in particular the hot electron behavior, to justify any DC life test developed for RF reliability assessment.…”

“…2 However, the comparison between DC and RF stress is always a matter of debate. [2][3][4][5] According to Joh et al, 3 RF stress degrades the device more severely than DC stress at the same bias point, and this effect increases with input power. The degradation has been attributed to trap formation due to hot carriers.…”

Compared deep class-AB and class-B ageing on AlGaN/GaN HEMT in S-Band pulsed-RF operating life

“…Further measurements (not shown) have been carried out to correlate these effects with respect to gate voltage. Actually, it has been noticed that drain voltage has quite no effect that proves that this gate lag phenomenon is related to surface traps [4,20,21]. Finally, same ware-out behaviours are obtained due to the trapping effects that weaken the quiescent drain current.…”

A Current-Transient Methodology for Trap Analysis for GaN High Electron Mobility Transistors

“…9, this time constant depends on temperature and is thermally activated with a very well defined activation energy E a = 0.57 eV. A trap at around this energy level with respect to the conduction band edge of the AlGaN is widely observed in DLTS and other transient techniques [21], [25], [35], [36]. This kind of trap was found to increase after device degradation [5], [21], [35], [36].…”