CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation

Kulshreshtha, Tanmai; Dhar, Anindya Sundar

doi:10.1007/s00034-018-0810-z

Cited by 10 publications

(9 citation statements)

References 21 publications

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“…Note that the sine/cosine values must be stored with a precision of 17 bits to compensate for rounding errors. The leaf M 0 provides the sines and cosines of the multiples of φ 0 = 2 0 φ = π/2 10 , while the leaf M 1 provides the sines and cosines of the multiples of φ 1 = 2 4 φ = π/2 6 . The greatest angle whose sine and cosine is stored in M 0 is 15π/2 10 .…”

Section: Leading Ones Of the Cosinementioning

confidence: 99%

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Using the complement of the cosine to compute trigonometric functions

Martos

Calderón

Chico

et al. 2020

EURASIP J. Adv. Signal Process.

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The computation of the sine and cosine functions is required in devices ranging from application-specific signal processors to general purpose floating-point units. Even in the latter case, the required functionality can be reduced to computing the sine and/or cosine of multiples of a constant angle. The latency of a sine/cosine generator can be reduced by using look-up tables. However, a direct implementation with look-up tables may be unfeasible if the input space is huge. In such a case, look-up tables with a number of entries lower than the size of the input space can be used indirectly. In previously published methods, the reduction in the number of table entries is obtained at the expense of increasing the table width and the computational cost. This paper introduces an alternative technique that makes it possible to reduce the size of the look-up tables as well as the required multiplications. The proposed technique can be used to implement sine/cosine generators of huge input space. It has been used to implement several twiddle factor generators in reconfigurable hardware and has enabled the number of look-up tables to be reduced by between 6 and 26% with respect to previous table-based techniques. Also, these implementations are about 50% faster than those based on Volder’s algorithm.

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Section: Leading Ones Of the Cosinementioning

confidence: 99%

“…• Generating the set of coefficients, called twiddle factors, of a discrete Fourier transform (DFT) [6]. The DFT of a complex sequence x of length L is another complex sequence X of the same length defined by X(k) = L−1 t=0 x(t)W tk L , where W L = e φi and φ = −2π/L.…”

Section: Introductionmentioning

confidence: 99%

Using the complement of the cosine to compute trigonometric functions

Martos

Calderón

Chico

et al. 2020

EURASIP J. Adv. Signal Process.

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“…where Fig. 2a shows the block diagram of the type-1 triangular windowed SDFT as per (12) and (13), where (12) corresponds to the feedback structure (FBS-A) and (13) corresponds to the feedforward structure (FFS). Now, we may apply modulation property over the time-domain expression in (12), by assuming another variable,…”

Section: Triangular Windowed Sdft Algorithmmentioning

confidence: 99%

“…The range of the initial angle of the rotational CORDIC is limited to

(][, - π / 2, π / 2)

. Therefore, to make further rotation outside this range, we usually pre‐rotate the initial vector by

π

(simply by changing the sign of the x and y components), so that the remaining rotation angle belongs to the standard range [13].…”

Section: Theorymentioning

confidence: 99%

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Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm

Kulshreshtha

Dhar

2019

IET Circuits, Devices & Systems

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This study presents a very-large-scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high-throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB.

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2022

Embedded Control for Mobile Robotic Applications

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CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation

Cited by 10 publications

References 21 publications

Using the complement of the cosine to compute trigonometric functions

Using the complement of the cosine to compute trigonometric functions

Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm

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