Copper pillar interconnect capability for mmwave applications in 3D integration technology

Joblot, S.; Bar, P.; Sibuet, H.; Ferrandon, C.; Reig, B.; Jan, S.; Arnaud, C.; Lamy, Yann; Coudrain, P.; Coffy, R.; Boillon, O.; Carpentier, J.F.

doi:10.1016/j.mee.2012.10.024

Cited by 18 publications

(5 citation statements)

References 10 publications

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“…4. The 3-D IC consists of two face to face stacked ICs connected with fine pitch copper pillars (μ-Cu-pillars) with 20 μm diameter, 40 μm pitch and less than 10 fF and 10 pH parasitic capacitance and inductance [11]. Such low parasitic inductance and capacitance do not limit the receiver and transmitter performance of our device.…”

Section: Silicon Photonics Hybrid Ic Overviewmentioning

confidence: 99%

Hybrid Silicon Photonic Circuits and Transceiver for 50 Gb/s NRZ Transmission Over Single-Mode Fiber

Denoyer

Cole

Santipo

et al. 2015

J. Lightwave Technol.

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This paper presents a 50 Gb/s per lane hybrid BiC-MOS and silicon photonic integrated circuit for use in fiber optic communications. Fine pitch copper pillars are used to integrate electronics and silicon photonics. The resulting device demonstrates the generation and detection of up to 56 Gb/s NRZ optical signals over 2-km standard single-mode fiber at 1310-nm wavelength. At 40 Gb/s, the link operates error free, and at 56 Gb/s well below KR4 RS-FEC operating BER. The power dissipation of TX including CW laser is 600 mW (450-mW driver, 150-mW CW laser), RX is 150 mW, resulting in total per channel of less than 750 mW.

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Section: Silicon Photonics Hybrid Ic Overviewmentioning

confidence: 99%

Hybrid Silicon Photonic Circuits and Transceiver for 50 Gb/s NRZ Transmission Over Single-Mode Fiber

Denoyer

Cole

Santipo

et al. 2015

J. Lightwave Technol.

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“…However, it has a high cost and still needs a larger area. To get a low-cost and high-density Cu interconnection for 3D stacks, 3D architecture with Cu pillar would be a good alternative to overcome the aforementioned TSV issue [ 22 ]. In this cross-point architecture (Figure 1 ), the Cu as an oxidize electrode or top electrode (TE) could be used; other inert electrodes such as tungsten (W) and titanium-nitride (TiN) or bottom electrode (BE) could be used; and Al 2 O 3 film could be used as switching layer.…”

Section: Introductionmentioning

confidence: 99%

Copper pillar and memory characteristics using Al2O3 switching material for 3D architecture

2014

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A novel idea by using copper (Cu) pillar is proposed in this study, which can replace the through-silicon-vias (TSV) technique in future three-dimensional (3D) architecture. The Cu pillar formation under external bias in an Al/Cu/Al2O3/TiN structure is simple and low cost. The Cu pillar is formed in the Al2O3 film under a small operation voltage of <5 V and a high-current-carrying conductor of >70 mA is obtained. More than 100 devices have shown tight distribution of the Cu pillars in Al2O3 film for high current compliance (CC) of 70 mA. Robust read pulse endurances of >106 cycles are observed with read voltages of −1, 1, and 4 V. However, read endurance is failed with read voltages of −1.5, −2, and −4 V. By decreasing negative read voltage, the read endurance is getting worst, which is owing to ruptured Cu pillar. Surface roughness and TiO x N y on TiN bottom electrode are observed by atomic force microscope and transmission electron microscope, respectively. The Al/Cu/Al2O3/TiN memory device shows good bipolar resistive switching behavior at a CC of 500 μA under small operating voltage of ±1 V and good data retention characteristics of >103 s with acceptable resistance ratio of >10 is also obtained. This suggests that high-current operation will help to form Cu pillar and lower-current operation will have bipolar resistive switching memory. Therefore, this new Cu/Al2O3/TiN structure will be benefited for 3D architecture in the future.

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“…But one of the bottlenecks of TSV is high cost and large integration area. Joblot et al [31] have reported the capability of Cu pillar for 3D interconnection technology. So, the conventional TSV technique of 3D FLASH can be also replaced by Cu pillar formation (i.e., stronger Cu filament in CBRAM structure) through 3D cross-point memory architecture for future below 11-nm technology node, which has been demonstrated previously [32].…”

Section: Introductionmentioning

confidence: 99%

Impact of device size and thickness of Al2O3 film on the Cu pillar and resistive switching characteristics for 3D cross-point memory application

et al. 2014

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Impact of the device size and thickness of Al2O3 film on the Cu pillars and resistive switching memory characteristics of the Al/Cu/Al2O3/TiN structures have been investigated for the first time. The memory device size and thickness of Al2O3 of 18 nm are observed by transmission electron microscope image. The 20-nm-thick Al2O3 films have been used for the Cu pillar formation (i.e., stronger Cu filaments) in the Al/Cu/Al2O3/TiN structures, which can be used for three-dimensional (3D) cross-point architecture as reported previously Nanoscale Res. Lett.9:366, 2014. Fifty randomly picked devices with sizes ranging from 8 × 8 to 0.4 × 0.4 μm2 have been measured. The 8-μm devices show 100% yield of Cu pillars, whereas only 74% successful is observed for the 0.4-μm devices, because smaller size devices have higher Joule heating effect and larger size devices show long read endurance of 105 cycles at a high read voltage of -1.5 V. On the other hand, the resistive switching memory characteristics of the 0.4-μm devices with a 2-nm-thick Al2O3 film show superior as compared to those of both the larger device sizes and thicker (10 nm) Al2O3 film, owing to higher Cu diffusion rate for the larger size and thicker Al2O3 film. In consequence, higher device-to-device uniformity of 88% and lower average RESET current of approximately 328 μA are observed for the 0.4-μm devices with a 2-nm-thick Al2O3 film. Data retention capability of our memory device of >48 h makes it a promising one for future nanoscale nonvolatile application. This conductive bridging resistive random access memory (CBRAM) device is forming free at a current compliance (CC) of 30 μA (even at a lowest CC of 0.1 μA) and operation voltage of ±3 V at a high resistance ratio of >104.

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Copper pillar interconnect capability for mmwave applications in 3D integration technology

Cited by 18 publications

References 10 publications

Hybrid Silicon Photonic Circuits and Transceiver for 50 Gb/s NRZ Transmission Over Single-Mode Fiber

Hybrid Silicon Photonic Circuits and Transceiver for 50 Gb/s NRZ Transmission Over Single-Mode Fiber

Copper pillar and memory characteristics using Al2O3 switching material for 3D architecture

Impact of device size and thickness of Al2O3 film on the Cu pillar and resistive switching characteristics for 3D cross-point memory application

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