Convex delay models for transistor sizing

Abstract

This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. The delay model is incorporated into a transistor sizing algorithm based on TILOS. The models were characterized by using a set of grid points and then validated using a disjoint data set. The models were found to be within about 10% of SPICE for nearly all of the gate types considered. Also presented are the experimental results of sizing various test circuits.

Timing analysis with compact variation-aware standard cell models

“…The table shows the maximum, average, and maximum of the averages of the residuals for each voltage point. It also includes the maximum of the average of the residuals for the 15 middle voltage points, which correspond to the 10-90% range of the transition, which is more critical for accurate timing analysis [35]. It was found that larger errors are associated with longer transitions and the tails of the waveforms.…”

Increase in delay uncertainty by performance optimization

“…We assume three models of gate delay uncertainties such that each gate delay fluctuates normally with 3C =5, 10 and 15% of its typical delay. In the case of a convex gate delay model for continuous transistor sizing, it is reported that 3C of the es- timation error in simple gates is 5 to 23% [11]. In this gate delay model, the error model of 3C =15% might be a reasonable assumption.…”

Robust gate sizing by Uncertainty Second Order Cone

“…The next step is to determine the Φ + and Φ − vectors collecting positive and negative terms in (27) respectively. According to the definition in (16), the components of Φ + and Φ − are extracted as follows:…”