Increase in delay uncertainty by performance optimization

Abstract

This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e. the delay of long paths are shortened and the delay of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which are caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statisticallydistributed circuit delay.

Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits

“…In case of a circuit whose delays of most paths are comparable, for example, the dependence on the inserted location becomes smaller. On the other hand, the mean of the delay variation of critical path becomes larger due to the statistical effect caused by the max operation [22] and hence the buffer delay should be determined according to a difference between the path delay where canary FF is inserted and the critical path delay with consideration for such statistical effect. Fig.…”

A case for exploiting complex arithmetic circuits towards performance yield enhancement

“…Figure 1 illustrates the dependence of the WID maximum critical path delay density function on the number of critical paths [5,8]. The horizontal axis indicates the delay and the vertical axis indicates the density.…”

“…In order to reduce the variability in circuit delay and hence to enhance performance yield, the well-known statistical features on circuit delay [5,8] should be exploited. Every circuit delay is strongly dependent upon the number of critical paths and the logic depth.…”

Power Valve: for low power operation and low stand-by power

“…Figure 1 (right) shows current waveforms of a 16 × 16 bit multiplier circuit. The power supply current rushes into the circuits when the clock cycle begins, because most paths are usually much shorter than the critical path [6]. With PV-1, the VGND voltage follows the current waveform.…”