Conversion from Synchronous RTL Models to Asynchronous RTL Models

RTL Conversion Method From Pipelined Synchronous RTL Models Into Asynchronous Ones

“…However, logic optimization considering the characteristics of asynchronous circuits cannot be performed, because logic synthesis is performed for synchronous Register Transfer Level (RTL) models with a clock constraint. We proposed a conversion method from synchronous RTL models into asynchronous ones in [22]. Compared to the GL conversion methods, we can optimize asynchronous circuits.…”

“…However, the RTL conversion method in [22] cannot deal with pipelined synchronous RTL models. Actually, pipelined synchronous circuits are used to improve the performance in many applications.…”

“…In this paper, we propose a conversion method from pipelined synchronous RTL models into pipelined asynchronous RTL models. The proposed method is an extension of [22]. To know which data-path resources in pipelined synchronous RTL models are controlled at each pipeline stage, we extend [22] to generate a control data flow graph (CDFG) from pipelined synchronous RTL models.…”

“…The proposed method is an extension of [22]. To know which data-path resources in pipelined synchronous RTL models are controlled at each pipeline stage, we extend [22] to generate a control data flow graph (CDFG) from pipelined synchronous RTL models. In addition, to deal with pipeline stalls, the proposed method generates a CDFG including conditions that pipeline stages stall the operations.…”

“…Section 3 describes asynchronous circuits with bundled-data implementation used in this work. Section 4 describes the overview of the RTL conversion method proposed in [22]. Section 5 describes the proposed RTL conversion method for pipelined synchronous RTL models.…”