Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL Models

Semba, Shogo; Saitō, Hiroshi; Tatsuoka, Masato; Fujimura, K.

doi:10.1587/transfun.2020vlp0004

Cited by 1 publication

(8 citation statements)

References 11 publications

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“…To obtain the high quality of asynchronous circuits, we used three optimization methods that can be applied during RTL conversion. One is the conversion from DFFs into D latches to reduce the dynamic power consumption of registers which is not described in [24]. Second is the use of appropriate DFFs to reduce the area of registers.…”

Section: Optimization Methodsmentioning

confidence: 99%

“…To solve this problem, [23] converts pipelined synchronous RTL models into pipelined asynchronous ones. However, there is a restriction that the input interval of pipeline circuits is one cycle in [24]. In this paper, there is no such restriction.…”

Section: Related Workmentioning

confidence: 97%

“…Compared to [21], we focus on the conversion from synchronous circuits into asynchronous circuits at RTL. This paper is an extension of [22]- [24]. [22] converts non-pipelined synchronous RTL models into non-pipelined asynchronous ones.…”

Section: Related Workmentioning

confidence: 99%

“…In this paper, there is no such restriction. On the other hand, [24] proposed optimization methods during the RTL conversion [22] to obtain the high quality of asynchronous circuits. In this paper, we also propose a conversion from DFFs to D latches to optimize the area of registers which is not described in [24].…”

Section: Related Workmentioning

confidence: 99%

“…To obtain the high quality of asynchronous circuits, we also propose optimization methods during the RTL conversion. The optimization methods are based on [24]. In addition, in this paper, we propose a new optimization method to convert DFFs into D latches to reduce the dynamic power consumption of registers.…”

Section: Introductionmentioning

confidence: 99%

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RTL Conversion Method From Pipelined Synchronous RTL Models Into Asynchronous Ones

Semba

Saitō

2022

IEEE Access

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In this paper, we propose a conversion method from pipelined synchronous Register Transfer Level (RTL) models into pipelined asynchronous RTL models with bundled-data implementation. To know data-path resources controlled by each pipeline stage, the proposed method generates a control data flow graph (CDFG) from synchronous RTL models. After generating the CDFG, the proposed method generates asynchronous RTL models by analyzing each pipeline stage on the CDFG, assigning asynchronous control modules, and connecting the control modules to the data-path resources. In addition, we also propose optimization methods during the conversion. In the experiment, we converted four pipelined synchronous RTL models into pipelined asynchronous ones. In addition, we performed logic synthesis for the converted asynchronous RTL models to check the quality of the asynchronous RTL models. The synthesized asynchronous circuits without the optimization methods could reduce the energy consumption by 1.47% on average compared to synchronous circuits. Moreover, the optimization methods could reduce the energy consumption by 15.12% on average compared to synchronous circuits.

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Section: Optimization Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 97%