Contributions to the evaluation of ensembles of combinational logic gates

Ribas, Renato P.; Bavaresco, Simone; Schuch, N.; Callegaro, Vinicius; Lubaszewski, Marcelo; Reis, André I.

doi:10.1016/j.mejo.2010.11.012

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Cited by 4 publications

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“…topologies of the same type of a sequential cell, since all delay arcs contribute to the oscillation frequency value [18]. The proposed structures can be seen as an extension of the methodology proposed by Ribas et al [19] [20] for combinational circuits to treat sequential circuits.…”

Section: Introductionmentioning

confidence: 94%

Ring oscillators for functional and delay test of latches and flip-flops

Ribas

Sun

Reis

et al. 2011

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design

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This work proposes a novel design strategy to use ring oscillators for functional validation and delay test of storage elements (latches and flip-flops). Besides the logic verification, power consumption and aging effect analysis can also be efficiently performed for the circuits under test. The proposed test solutions are also quite suitable for self-timed and self-checking full verification of latches and flip-flops, as well as for comparing different implementations of such sequential cells. This test approach has been validated at the gate level by using HDL descriptions as well as at the transistor level through electrical simulations.

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Section: Introductionmentioning

confidence: 94%