Content Addressable Memory Based Binarized Neural Network Accelerator Using Time-Domain Signal Processing

Choi, Woong; Jeong, Kwanghyo; Choi, Kyungrak; Lee, Kyeongho; Park, Jongsun

doi:10.1109/dac.2018.8465903

Cited by 7 publications

(18 citation statements)

References 5 publications

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“…This is a major differentiator when compared with the state-of-the-art NN-based AI. Table 4 compares the Tsetlin machine energy efficiency with three recently reported NN approaches: a mixed-signal neuromorphic approach using time-domain arithmetic organized in a spatially unrolled neuron architecture [25], a low-power FPGA-based convolutional BNN (CBNN) approach that uses exclusive NOR (XNOR) adder-based integer weight biases to reduce the arithmetic-heavy batch normalization for synchronization between the deeper layers [26] and finally an in-memory BNN approach using parallel content-addressable memories (CAMs) to reduce the frequent data movement costs [27]. Our comparative analysis considered disparities between these approaches in terms of (i) their internal structures in both combinational and sequential parts and (ii) the size of datasets used to validate the efficiencies.…”

Section: Performance and Energy Efficiencymentioning

confidence: 99%

Learning automata based energy-efficient AI hardware design for IoT applications

Wheeldon

Shafik

Rahman

et al. 2020

Phil. Trans. R. Soc. A.

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Energy efficiency continues to be the core design challenge for artificial intelligence (AI) hardware designers. In this paper, we propose a new AI hardware architecture targeting Internet of Things applications. The architecture is founded on the principle of learning automata, defined using propositional logic. The logic-based underpinning enables low-energy footprints as well as high learning accuracy during training and inference, which are crucial requirements for efficient AI with long operating life. We present the first insights into this new architecture in the form of a custom-designed integrated circuit for pervasive applications. Fundamental to this circuit is systematic encoding of binarized input data fed into maximally parallel logic blocks. The allocation of these blocks is optimized through a design exploration and automation flow using field programmable gate array-based fast prototypes and software simulations. The design flow allows for an expedited hyperparameter search for meeting the conflicting requirements of energy frugality and high accuracy. Extensive validations on the hardware implementation of the new architecture using single- and multi-class machine learning datasets show potential for significantly lower energy than the existing AI hardware architectures. In addition, we demonstrate test accuracy and robustness matching the software implementation, outperforming other state-of-the-art machine learning algorithms. This article is part of the theme issue ‘Advanced electromagnetic non-destructive evaluation and smart monitoring’.

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Section: Performance and Energy Efficiencymentioning

confidence: 99%

Learning automata based energy-efficient AI hardware design for IoT applications

Wheeldon

Shafik

Rahman

et al. 2020

Phil. Trans. R. Soc. A.

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“…This section presents the proposed DWM-based BNN convolutional layer design [30]. For the implementation of the parallel XNOR-popcount operation with DWM, the DWM input buses and the DWM-based weight reorder blocks for filter sliding operations will be discussed with specific examples.…”

Section: Dwm Based Bnn Convolutional Layer Designmentioning

confidence: 99%

“…17(c). In the proposed design, to reduce the memory access in filter sliding operations, the DWM-based cell array performs the parallel XNOR-popcount operation [30].…”

Section: B Dwm Based Cell Array For Bnnmentioning

confidence: 99%

Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers

et al. 2020

Self Cite

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In the hardware implementation of deep learning algorithms such as, convolutional neural networks (CNNs) and binarized neural networks (BNNs), multiple dot products and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a domain wall memory (DWM) based design of CNN and BNN convolutional layers. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and energy cost of DWM-based design for filter sliding. Simulation results with 65 nm CMOS process show 45% and 43% of energy savings compared to the conventional CNN and BNN design approach, respectively. INDEX TERMS Binarized neural network, convolutional neural network, deep neural network, domain wall memory.

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“…The versatility of RRAM devices extends to their ability to be organized in crossbar-like structures, which have found applications in various computing paradigms, including analog computing for neural network implementations 10,11 , digital logic computing 12 , and spiking neural network architectures 13,14 . Notably, RRAM devices demonstrate efficient performance in critical operations such as vector-matrix-multiplication (VMM), crucial for neural network implementations, with a constant computational complexity of O(1) regardless of the input vector's size 15 .…”

Section: Introductionmentioning

confidence: 99%

Sequence Detection in Bilayer 1T1R RRAM Device with Integrated State Machine

Singh,

Paul,

Bende

et al. 2024

Preprint

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Recent advancements in machine learning algorithms have driven a search for novel computation hardware and techniques to alleviate data bottlenecks. In terms of hardware, there’s a noticeable trend towards in-memory computing (IMC). Resistive random-access memory (RRAM) has surfaced as a compelling option for IMC applications owing to its non-volatile nature, reduced power requirements, and more compute density in contrast to conventional CMOS-based computing approaches. Simultaneously, there has been a notable rise in the advancement of novel algorithms alternatives to neuron-based implementations based on learning automata (e.g., propositional logic-based Tselin machine), presenting resource efficiency, particularly within the domain of the state-machine paradigm. An important observation is the multi-level behavior exhibited by RRAM cells, offering an avenue to mimic state machine functionalities. However, integrating state machines onto RRAM devices poses challenges despite these advancements. Through experimental explorations, this paper investigates the practical utilization of RRAM’s multi-state properties for finite-state machine (FSM) applications. This study demonstrates the multi-state behavior through gradual reset methodologies by fabricating RRAM cells alongside CMOS transistors to create 1T1R cells. Moreover, a sequence detector is devised to identify specific patterns within strings using a single 1T1R cell, effectively encapsulating the FSM onto a single device. This approach promises improvements in data density and offers enhanced energy efficiency. Rigorous experimental validation underscores the accuracy and reliability of the proposed methodology, laying a robust groundwork for efficient multi-state applications within advanced computing paradigms.

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Content Addressable Memory Based Binarized Neural Network Accelerator Using Time-Domain Signal Processing

Cited by 7 publications

References 5 publications

Learning automata based energy-efficient AI hardware design for IoT applications

Learning automata based energy-efficient AI hardware design for IoT applications

Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers

Sequence Detection in Bilayer 1T1R RRAM Device with Integrated State Machine

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