Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers

Chung, Jihoon; Choi, Woong; Park, Jongsun; Ghosh, Swaroop

doi:10.1109/access.2020.2968081

Cited by 5 publications

(2 citation statements)

References 21 publications

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“…Finally, DWM technology has been also used in general-purpose GPUs to design register files [3,20,23,43] and caches [4,38], as well as in convolutional and recurrent neural network accelerators to implement on-chip memories [9,10,18,30,42].…”

Section: Related Workmentioning

confidence: 99%

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Tárrega

Valero

Lorente

et al. 2022

Proceedings of the 36th ACM International Conference on Supercomputing

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First-level (L1) caches have been traditionally implemented with Static Random-Access Memory (SRAM) technology, since it is the fastest memory technology, and L1 caches call for tight timing constraints in the processor pipeline. However, one of the main downsides of SRAM is its low density, which prevents L1 caches to improve their storage capacity beyond a few tens of KB. On the other hand, the recent Domain Wall Memory (DWM) technology overcomes such a constraint by arranging multiple bits in a magnetic racetrack, and sharing a header to access those bits. Accessing a bit requires a shift operation to align the target bit under the header. Such shifts increase the final access latency, which is the main reason why DWM has been mostly used to implement slow last-level caches.This paper proposes a novel DWM-based L1 cache data array design, namely Fast-Track Cache (FTC), that allows L1 caches with bigger storage capacities while reducing the shift overhead thanks to an enhanced exploitation of spatial and temporal localities.Experimental results show that most FTC accesses do not require shifts. As a consequence, and due to its larger capacity, FTC improves the processor performance on average by 15% over a conventional SRAM memory subsystem and the state-of-the-art TapeCache architecture based on DWM. At the same time, energy savings are improved on average by 34% over the conventional design. CCS CONCEPTS• Hardware → Spintronics and magnetic technologies; Memory and dense storage.

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Section: Related Workmentioning

confidence: 99%

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Tárrega

Valero

Lorente

et al. 2022

Proceedings of the 36th ACM International Conference on Supercomputing

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“…The main challenges in using CNNs are latency and memory access [15], [16], due to tens to hundreds of megabyte parameters and operations which require data movement between on-chip and off-chip to support the computation. In edge applications such as smart sensors, wearable and autonomous devices, security and latency are important considerations [17], [18].…”

Section: Introductionmentioning

confidence: 99%

SLIT: An Energy-Efficient Reconfigurable Hardware Architecture for Deep Convolutional Neural Networks

Tran

Nakashima

2020

IEICE Trans. Electron.

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Convolutional neural networks (CNNs) have dominated a range of applications, from advanced manufacturing to autonomous cars. For energy cost-efficiency, developing low-power hardware for CNNs is a research trend. Due to the large input size, the first few convolutional layers generally consume most latency and hardware resources on hardware design. To address these challenges, this paper proposes an innovative architecture named SLIT to extract feature maps and reconstruct the first few layers on CNNs. In this reconstruction approach, total multiplyaccumulate operations are eliminated on the first layers. We evaluate new topology with MNIST, CIFAR, SVHN, and ImageNet datasets on image classification application. Latency and hardware resources of the inference step are evaluated on the chip ZC7Z020-1CLG484C FPGA with Lenet-5 and VGG schemes. On the Lenet-5 scheme, our architecture reduces 39% of latency and 70% of hardware resources with a 0.456 W power consumption compared to previous works. Even though the VGG models perform with a 10% reduction in hardware resources and latency, we hope our overall results will potentially give a new impetus for future studies to reach a higher optimization on hardware design. Notably, the SLIT architecture efficiently merges with most popular CNNs at a slightly sacrificing accuracy of a factor of 0.27% on MNIST, ranging from 0.5% to 1.5% on CI-FAR, approximately 2.2% on ImageNet, and remaining the same on SVHN databases.

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Exploring Versatility of Primary Visual Cortex Inspired Feature Extraction Hardware Model through Various Network Architectures

Tran

Nakashima

2021

2021 International Conference on Computing, Electronics &Amp; Communications Engineering (iCCECE)

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Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers

Cited by 5 publications

References 21 publications

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Fast-track cache

SLIT: An Energy-Efficient Reconfigurable Hardware Architecture for Deep Convolutional Neural Networks

Exploring Versatility of Primary Visual Cortex Inspired Feature Extraction Hardware Model through Various Network Architectures

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