Sequence Detection in Bilayer 1T1R RRAM Device with Integrated State Machine

Abstract

Recent advancements in machine learning algorithms have driven a search for novel computation hardware and techniques to alleviate data bottlenecks. In terms of hardware, there’s a noticeable trend towards in-memory computing (IMC). Resistive random-access memory (RRAM) has surfaced as a compelling option for IMC applications owing to its non-volatile nature, reduced power requirements, and more compute density in contrast to conventional CMOS-based computing approaches. Simultaneously, there has been a notable rise in the advancement of novel algorithms alternatives to neuron-based implementations based on learning automata (e.g., propositional logic-based Tselin machine), presenting resource efficiency, particularly within the domain of the state-machine paradigm. An important observation is the multi-level behavior exhibited by RRAM cells, offering an avenue to mimic state machine functionalities. However, integrating state machines onto RRAM devices poses challenges despite these advancements. Through experimental explorations, this paper investigates the practical utilization of RRAM’s multi-state properties for finite-state machine (FSM) applications. This study demonstrates the multi-state behavior through gradual reset methodologies by fabricating RRAM cells alongside CMOS transistors to create 1T1R cells. Moreover, a sequence detector is devised to identify specific patterns within strings using a single 1T1R cell, effectively encapsulating the FSM onto a single device. This approach promises improvements in data density and offers enhanced energy efficiency. Rigorous experimental validation underscores the accuracy and reliability of the proposed methodology, laying a robust groundwork for efficient multi-state applications within advanced computing paradigms.