Contact resistance to SrRuO3 and La0.67Sr0.33MnO3 epitaxial films

Abstract

Contact resistance to the metallic oxide electrodes, SrRuO3 (SRO) and La0.67Sr0.33MnO3 (LSMO), is an important parameter that affects the ferroelectric tunnel junction (FTJ) device performance. We have systematically studied the contact resistance between metallic oxide electrodes (SRO, LSMO) and contact metal overlayers (Ti, Pt) after exposure to various processing environments. Specific contact resistivity (ρc) for Ti and Pt contact metals and the sheet resistance (Rsh) of the metallic oxides are measured after exposure to different reactive ion plasma process steps. Sheet resistance degradation was observed for both SRO and LSMO films after exposure to plasma treatment. Severe contact resistance degradation was observed for Ti contacts as compared to Pt after reactive ion etching on LSMO films. The effect of oxygen (O2) plasma on LSMO was observed to be most severe with non-ohmic behavior with Ti contacts, which can affect the functionality of FTJ devices. Finally, the thermal stability of contacts was investigated, Pt contacts to SRO show low resistance ohmic behavior even after annealing at 900 °C, making it a suitable contact for FTJ devices.

Free-standing La0.7Sr0.3MnO3 suspended micro-bridges on buffered silicon substrates showing undegraded low frequency noise properties

“…They served as an additional Protecting Layer (PL) in order to strengthen the suspended micro-bridges in the case of thin LSMO layers (Figure 1-c). Figure 1-d Achieving low resistive ohmic contacts on LSMO is quite challenging and has to be carefully optimized before considering any use of LSMO thin films in devices [51]. Electrical contacts must not only be ohmic and low resistive but they have to adhere to the LSMO surface without damaging its properties.…”

A Robust Memristor Based on Epitaxial Vertically Aligned Nanostructured BaTiO3−CeO2 Films on Silicon

“…Among of them, BaTiO 3 (BTO) is one of the best substitutes for ferroelectric perovskite−oxide−lead‐based materials due to the technical demand for ferroelectric materials and the environmental requirements for lead‐free and non‐toxic materials. However, most of ferroelectric materials were grown on the single crystal substrate, and the lack of silicon compatibility of complex oxide materials [ 12 ] impedes the practical integration of the FTJ with current silicon complementary metal−oxide−semiconductor technology. On the other hand, the memristor performance and the physical mechanism need to be further enhanced and clarified.…”

Sub-100 nm integrated ferroelectric tunnel junction devices using hydrogen silsesquioxane planarization

“…The ultrathin ferroelectric oxide layer, which is embedded inside M 1 -I-M 2 structure, makes the integration challenging, and it requires reactive ion etching of the layers and stopping on the bottom metal (M 2 ) layer with minimal ion damage. Ion damage of the bottom metal is shown to affect the conductivity of the layer 19 and hence the device performance. 20 Moreover, as FTJ comprises perovskite oxide materials such as SrRuO 3 (SRO), La 0.67 Sr 0.33 MnO 3 , and BTO, it must be processed at low temperature to avoid device degradation during metal contact formation.…”

“…20 Moreover, as FTJ comprises perovskite oxide materials such as SrRuO 3 (SRO), La 0.67 Sr 0.33 MnO 3 , and BTO, it must be processed at low temperature to avoid device degradation during metal contact formation. 19 Recently, fully integrated $300 Â 300 nm 2 FTJ memory based on Co/BTO/SRO heterostructure has been reported; 15 however, fabrication of sub-100 nm FTJ memory using the same process faces serious difficulties due to the sub-50 nm critical alignment between the contact pad to the nanoscale top contact. A new low temperature fabrication method is required to integrate sub-100 nm FTJ that eliminates steps of critical alignments, and this could be achieved with the planarization of the wafer with insulating low-k dielectric layers.…”