Constraint generation for routing analog circuits

Choudhury, Umakanta; Sangiovanni‐Vincentelli, Alberto

doi:10.1145/123186.123403

Cited by 32 publications

(15 citation statements)

References 6 publications

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“…Constraints for layout design and optimization [4][5][6][7][ [16][17][18][19][20][21][ [23][24][25][26][27][28][29][30][31][32][33][34][35][36] include the symmetry constraints for devices, direct current path branches, direct current paths, blocks and upper level circuits, the matching constraints for group of devices, the neighboring constraints, the protection constraints, the signal path and sequence constraints for direct current paths, and the direct current path and power reaching sequence constraints for group of devices. The symmetry constraints can be used for minimizing the mismatch by mirroring placement of devices, direct current path branches, direct current paths, blocks, or upper level circuits, and mirroring the wiring of interconnections to reduce the mismatch on devices and the mismatch on wires, in further to reduce mismatch on direct current path branches, direct current paths, blocks and upper level circuits during layout design and optimization, and such constraints can be gotten with encoding based symmetry direction.…”

Section: Layout Constraint Knowledgementioning

confidence: 99%

Analog-Aware Schematic Synthesis

Wu¹

2011

Advances in Analog Circuits

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Section: Layout Constraint Knowledgementioning

confidence: 99%

Analog-Aware Schematic Synthesis

Wu¹

2011

Advances in Analog Circuits

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“…In order to derive , (8) is differentiated on both hand-sides and solved with respect to . Using the fact that vanishes, we obtain (23) Using the definition of (24) where is computed using (23). Now, only the derivative , i.e., , remains to be computed.…”

Section: A Sensitivity Analysismentioning

confidence: 99%

“…The sensitivity of a given performance is computed with respect to the parameters related to each noise source acting on every node in the analog modules being placed. In step 1), a set of bounds is generated for a subset of critical nodes using constrained optimization techniques [23] and the specification on the maximum positive and negative performance degradation . Subset is generated from the cumulative impact of all parasitic noise sources acting on each node as in [23].…”

Section: Placement Problemmentioning

confidence: 99%

“…Sensitivities with respect to all parasitics (RC for interconnect and for substrate receptors) were computed. Then, constraint generator PARCAR [23], [19] was used to derive a minimal set of constraints on the maximum admissible noise voltage in each one of the receptors and on the maximum R/C values for the interconnect parasitics in the VCO. The CPU time needed for the sensitivity analysis and constraint calculation was in total 2545 s, the results are shown in Table II.…”

Section: A Physical Designmentioning

confidence: 99%

See 1 more Smart Citation

Substrate optimization based on semi-analytical techniques

Charbon

Gharpurey

Meyer

et al. 1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Several methods are presented for highly efficient calculation of substrate noise transport in integrated circuits. A three-dimensional Green's function-based boundary element method, accelerated through use of the fast Fourier transform, allows the computation of sensitivities with respect to all substrate parameters at a considerably higher speed than any methods reported in the literature. Substrate sensitivities are used in a number of physical optimization tools, such as placement and trend analysis. The aim is a fast and accurate estimation of the impact of technology migration and/or layout redesign on substrate noise and, ultimately, on the circuit's overall performance. The suitability of the approach is shown through industrial-strength mixed-mode integrated circuits fabricated on a standard CMOS process.Index Terms-Boundary element methods, convergence of numerical methods, discrete Fourier transients, integrated circuit noise, noise, noise generators, noise measurement, numerical analysis, numerical stability, optimization methods, phase noise, sensitivity, semiconductor device noise, switching circuits, switching transients.

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“…Sensitivities can also be used to generate a set of constraints on interconnectparasitics [3]. A number of techniques have been proposed for a constraint-based approach to the layoutof analog ICs [3,4,5,6,7]. In these approachesa constraint generator is used to map high-level performance specifications onto a set of bounds, which are then used during the synthesis phases to control layout parasitics.…”

Section: Introductionmentioning

confidence: 99%

Generalized constraint generation in the presence of non-deterministic parasitics

Charbon¹,

Miliozzi²,

Malavasi³

et al.

Proceedings of International Conference on Computer Aided Design

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In ci constraint-driven layout synthesis erivironnient, parasitic constraints clre generated and iinpleiiieiited in each phase of the design process to meet a given set of peglonnance specifications. The success of the synthesis phase depends in greatpart on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a nitniber of parasitic effects in active and passive devices due to non-deterininistic process variations. To address this problem a novel nietliodology is proposed based on the separation of d l variables cusociated with non-detenninistic parmitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements of the method are n well-dejked set of statistical properties for all parasitics and a reasonable degree of linearity of the perfbnnance measures relevant to design.

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Constraint generation for routing analog circuits

Cited by 32 publications

References 6 publications

Analog-Aware Schematic Synthesis

Analog-Aware Schematic Synthesis

Substrate optimization based on semi-analytical techniques

Generalized constraint generation in the presence of non-deterministic parasitics

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