In ci constraint-driven layout synthesis erivironnient, parasitic constraints clre generated and iinpleiiieiited in each phase of the design process to meet a given set of peglonnance specifications. The success of the synthesis phase depends in greatpart on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a nitniber of parasitic effects in active and passive devices due to non-deterininistic process variations. To address this problem a novel nietliodology is proposed based on the separation of d l variables cusociated with non-detenninistic parmitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements of the method are n well-dejked set of statistical properties for all parasitics and a reasonable degree of linearity of the perfbnnance measures relevant to design.
4 novel methodology for circuit design and automatic layout generition is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced noise. Accurate and efficient zvaluiitionof the circuit during designis possible by takig into account such non-idealities. Techniques are presented to derive and use a set of constraints on substrate noise and on the geometric instances of the Layout. Verification is performed using substrate extraction in combination with parasitic estimation techniques. To show the suitability of the approach, a VCO for a PLL has been designed and implemented in a CMOS 1 Fm technology. The circuit has been optimized both at the schematic and at the layout level for power and performance, while its sensilivity to layout parasitics and substrate noise has been minimized.
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