Considerations for the use of defocus models for OPC

Sturtevant, John L.; Torres, J. Andres; Word, James; Granik, Yuri; LaCour, Pat

doi:10.1117/12.598059

Cited by 15 publications

(10 citation statements)

References 2 publications

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“…A more practical approach is to design the photomask in a way that renders the results less sensitive to process variations. Several researchers made contributions in this direction [10][11][12][13]. We offer an advancement of this concept where the photomask is synthesized by minimizing a cost function that embodies the design goals including invariance with respect to process parameters.…”

Section: Introductionmentioning

confidence: 99%

Sequential PPC and process-window-aware mask layout synthesis

Sezginer¹,

Zach²,

Yenikaya³

et al. 2006

SPIE Proceedings

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We present a full-chip implementation of model-based process and proximity compensation. Etch corrections are applied according to a two-dimensional model. Lithography is compensated by optimizing a cost function that expresses the design intent. The cost function penalizes edge placement errors at best dose and defocus as well as displacement of the edges in response to a specified change in a process parameter. This increases immunity to bridging in low contrast areas.

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Section: Introductionmentioning

confidence: 99%

Sequential PPC and process-window-aware mask layout synthesis

Sezginer¹,

Zach²,

Yenikaya³

et al. 2006

SPIE Proceedings

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“…For 90 nm technology and beyond, ORC begins to penetrate the productive environment. A variety of EDAvendor specific ORC implementations [1][2][3][4] has already successfully prevented the generation of masks containing non-printable features and, as a consequence, saved considerable time and expenses for their customers. For the next technology generations, ORC will become an indispensable simulation tool whose capabilities with respect to simulation of vectorial effects and thick masks have to be successively extended [5].…”

Section: Introductionmentioning

confidence: 99%

ORC and LfD as first steps towards DfM

Marz

Peter

Maurer

2006

22nd European Mask and Lithography Conference

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“…Although the extent of variation is tolerable within the process window, the linewidth deviation can translate to performance and power variations at the design level. The use of defocus models (e.g., by Sturtevant et al [2]) instead of the best focus model improves the linewidth response after OPC. However, post-OPC linewidths still vary with focus since the OPC is valid only at a single focus condition.…”

Section: Motivationmentioning

confidence: 99%

Electrical metrics for lithographic line-end tapering

et al. 2008

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Despite advanced resolution enhancement techniques (RET) and illumination techniques, several sources of variation in the pattern transfer process manifest as variations in chip-level performance and power. At 45nm and below, accurate design-level performance and power analyses must consider litho-simulated non-idealities. However, lithography simulation is computationally expensive to perform at chip-scale, and essentially infeasible during iterative design optimization. In this work, we develop a predictive model of device linewidths after optical proximity correction (OPC) across the process window. The predictive model is fast, accurate and highly scalable, enabling its use in the design phase at full-chip scale without actually performing OPC and litho simulation.To model litho effects on 2D poly geometries in standard cell layouts, we rigorously identify layout parameters that affect the litho contour. We classify gate poly (devices) into different categories based on their geometric parameters as well as those of neighboring field poly shapes. To create a model, we create a design of experiments (DOE) for all device categories and perform OPC followed by through-process window litho simulation. To limit the runtime of OPC and litho simulation for the DOE, we reduce the layout parameter space with a rigorously qualified methodology for filtering out unimportant parameters. To allow prediction of the device contour, we model the device edge placement error (EPE) using a response surface methodology followed by polynomial regression. We have implemented our predictive linewidth modeling with foundry 90nm and 65nm technology, along with industry-strength OPC models and recipes. Using the regression models, we have performed prediction on standard-cell blocks and achieved a 3σ prediction accuracy of 2nm across the process window.

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Considerations for the use of defocus models for OPC

Cited by 15 publications

References 2 publications

Sequential PPC and process-window-aware mask layout synthesis

Sequential PPC and process-window-aware mask layout synthesis

ORC and LfD as first steps towards DfM

Electrical metrics for lithographic line-end tapering

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