Electrical metrics for lithographic line-end tapering

Abstract

Despite advanced resolution enhancement techniques (RET) and illumination techniques, several sources of variation in the pattern transfer process manifest as variations in chip-level performance and power. At 45nm and below, accurate design-level performance and power analyses must consider litho-simulated non-idealities. However, lithography simulation is computationally expensive to perform at chip-scale, and essentially infeasible during iterative design optimization. In this work, we develop a predictive model of device linewidths after optical proximity correction (OPC) across the process window. The predictive model is fast, accurate and highly scalable, enabling its use in the design phase at full-chip scale without actually performing OPC and litho simulation.To model litho effects on 2D poly geometries in standard cell layouts, we rigorously identify layout parameters that affect the litho contour. We classify gate poly (devices) into different categories based on their geometric parameters as well as those of neighboring field poly shapes. To create a model, we create a design of experiments (DOE) for all device categories and perform OPC followed by through-process window litho simulation. To limit the runtime of OPC and litho simulation for the DOE, we reduce the layout parameter space with a rigorously qualified methodology for filtering out unimportant parameters. To allow prediction of the device contour, we model the device edge placement error (EPE) using a response surface methodology followed by polynomial regression. We have implemented our predictive linewidth modeling with foundry 90nm and 65nm technology, along with industry-strength OPC models and recipes. Using the regression models, we have performed prediction on standard-cell blocks and achieved a 3σ prediction accuracy of 2nm across the process window.

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

“…This effect becomes pronounced when considering lineend pull-back and poly-to-diffusion overlay error. The tapered shape and gate length at the transistor edge are described using the model offered in [16] 12 while accounting for line-end pullback (mean value) and overlay errors (from distribution). Lineends are assumed to extend beyond the gate as far as possible unless the user enforces minimum line-end extension (LEE) rule for the entire layout.…”

“…Finally, for 40nm wiring pitch, only a 1D layout with SADP is possible. For STE, we assume a tip-to-tip spacing rule equal to the minimum spacing in our study 16 . PS-DPT and SADP impose peculiar layout restrictions, however, and many patterns cannot be formed with these technologies (see examples of Figure 25).…”

“…ST-DPL essentially consists of applying a translational mask shift to re-use the same pho- 16 Implying that the minimum linewidth of the trim mask is the same as that of the first exposure mask. tomask for both exposures of DPT and removing extra printed features using a non-critical trim exposure.…”

“…Several published works have done empirical "one-at-a-time" evaluation of design rules [12,15]. For example, the work in [16] electrically evaluates line-end extension rule and conclude that it may be too conservative. Other recent works [17,18] offer solutions to explore DRs from a pure printability perspective and do not examine the effects of DRs on circuit characteristics.…”

Trapezoidal approximation for on-current modeling of 45-nm non-rectilinear gate shape

“…Thus far, several post-lithographic simulation (PLS) techniques that can handle NRG transistors have been proposed [3,4,5,6,7]. Most of these techniques are based on a gate slicing method and an equivalent gate length (EGL) method, which use the summation of I on and I of f in each slice after uniformly partitioning a given device channel into small slices.…”