Considerations for Static Energy Reduction in Digital CMOS ICs Using NEMS Power Gating

Sankar, Sivaneswaran; Kumar, Ulayil Sajesh; Goel, Mayank; Baghini, Maryam Shojaei; Rao, V. Ramgopal

doi:10.1109/ted.2017.2656802

Cited by 14 publications

(2 citation statements)

References 8 publications

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“…Efficiency of GDI technique can be improved by using Mixed Threshold Voltage (MVT) scheme [31]. Circuit structures with different applied clocks can also help in achieving power and speed efficiency [32][33]. Transistor gating techniques can also be used for power reduction but it suffers from poor reliability due to ground bounce problem which can further be overcome by sleep transistor [34].…”

Section: Previous Contributionmentioning

confidence: 99%

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sharma*,

Sohal

2019

IJITEE

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In this paper we propose a power efficient technique called Sleepy- Gate Diffusion Input (S-GDI) that can be used for efficient digital design at nano scale foundries. For area and power comparison, ten prior techniques are taken in to consideration and applied on XOR gate, 1-bit adder, 1-bit comparator and 4- bit up-down counter. All techniques are parametrically analyzed on 65nm technology. The proposed S-GDI technique has been observed power efficient as compared to Complementary CMOS technique (CCT), Complementary Pass Transistor Logic (CPTL), DCMOS (Differential CMOS), Differential Cascode Voltage Switch with Pass Gate Logic (DCVSPG), Energy Economized Pass Transistor Logic (EEPL), Lean Integration with Pass Transistors (LEAP), Push-Pull Pass Transistor Logic (PPL), Pass Transistor Logic (PTL), CMOS with Transmission Gate (TG) and Gate diffusion Input (GDI). As compared to GDI technique S-GDI is showing 96.20%, 93.65%, 97.88% and 98.22% power efficiency for XOR, 1-bit adder, 1-bit comparator and 4-bit up-down counter respectively. S-GDI is showing area efficiency of 17.16% and 28.1% for XOR, 41.26% and 53.89% for 1-bit adder, 7.6% and 21.76% for 1-bit comparator and 6.7% and 28% for up-down counter over EEPL and DCMOS technique respectively. Although other techniques except EEPL and DCMOS techniques are area efficient as compared to proposed technique but this is on the expense of higher total power dissipation. So, PDP (power delay products) of all considered techniques are also calculated on 65nm technology for both SUM and CARRY outputs of 1-bit adder. In both cases power delay product for S-GDI technique is very less as compared to all other considered technique. Due to efficiency of S-GDI in terms of considered parameters, this technique can be efficiently used for low power applications

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Section: Previous Contributionmentioning

confidence: 99%

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sharma*,

Sohal

2019

IJITEE

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“…The leakage current is particularly important in mobile devices, where the battery lifetime is decided by their leakage during sleep time. To mitigate the leakage current, a number of low-leakage techniques have been developed for many years [3][4][5][6]. Among them, power gating techniques have been used widely for many years, where leakage current can be cut off by an NMOS header or PMOS footer with high threshold voltage [7].…”

Section: Introductionmentioning

confidence: 99%

Comparative Study on Power Gating Techniques for Lower Power Delay Product, Smaller Power Loss, Faster Wakeup Time

Vo¹

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

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The power gating is one of the most popular reduction leakage techniques. We make comparison among various power gating schemes in terms of power delay product, energy loss, and wake-up time using the 45-nm Predictive Technology Model. In my conclusion, the Dual-Switch Power Gating (DSPG) shows lower power delay product, smaller energy loss, faster wake-up time than the other power gating schemes such as the Single-Switch and Charge-Recycled Power Gating schemes. Based on these advantages, the DSPG is suggested in this paper as a viable candidate suitable to a fine-grain leakage control scheme, where logic blocks go in and out very frequently and shortly between the active and sleep modes.

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Wafer‐Scale CMOS‐Compatible Electro‐Thermally Actuated Nanomechanical Non‐Volatile Switch with Out‐of‐Plane Electrode Configuration

Lee,

Choi,

Kang

et al. 2024

Adv Elect Materials

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The rapid growth of data‐intensive applications has significantly heightened the concerns about power consumption in current computing systems. From this perspective, there have been substantial efforts to implement ultra‐low power systems by integrating nanoelectromechanical non‐volatile switches (NEM‐NVS) with near‐zero leakage current into standard complementary metal‐oxide‐semiconductor (CMOS) circuits. To practically harness the potential of the NEM‐NVS, it is imperative to achieve high performance, such as low voltage, high on/off ratio, and high reliability, while simultaneously ensuring wafer‐scale CMOS compatibility. However, achieving these requirements is still challenging, primarily due to their electrostatic operation, in‐plane electrode configuration, and conventional fabrication methods. Here, an electro‐thermally actuated nanomechanical non‐volatile switch (ETAN‐NVS) with an out‐of‐plane electrode configuration along with an 8‐inch wafer‐scale CMOS‐compatible fabrication method is reported. By introducing the electrothermal mechanism into a vertically actuated buckling nanostructure, the fabricated ETAN‐NVS attains CMOS‐level voltage (<2.4 V), a high on/off ratio (>108), and exceptional reliability (>1300 cycles). Moreover, a successful wafer‐scale demonstration of the ETAN‐NVS using only a CMOS‐compatible process paves the way for 3D integration with CMOS logic.

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Considerations for Static Energy Reduction in Digital CMOS ICs Using NEMS Power Gating

Cited by 14 publications

References 8 publications

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Comparative Study on Power Gating Techniques for Lower Power Delay Product, Smaller Power Loss, Faster Wakeup Time

Wafer‐Scale CMOS‐Compatible Electro‐Thermally Actuated Nanomechanical Non‐Volatile Switch with Out‐of‐Plane Electrode Configuration

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