Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI

Saldaña, Manuel; Nunes, D. C.; Ramalho, E.; Chow, Paul

doi:10.1109/reconf.2006.307779

Cited by 18 publications

(12 citation statements)

References 14 publications

(15 reference statements)

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“…RELATED WORK TMD-MPI was created with the influence of the Multiprocessor System-on-Chip [26] and Network-on-Chip research fields. Related work of those areas to TMD-MPI is discussed in previous work [8] [9] and briefly mentioned in Section VI-B. In this Section, current APIs for X86-FPGA communication are compared with TMD-MPI.…”

Section: An Example Of Portability and Scalabilitymentioning

confidence: 99%

“…Currently, there is no implemented standard API for a high-level parallel programming model that includes the interaction between X86 processors and FPGAs. There is, however, interesting progress done by the OpenFPGA [6] organization on this matter, which is compared against this work in Section V. Previous work proposed TMD-MPI [7][8] [9][10] as a subset implementation of the MPI standard targeting Multiprocessor System-on-Chip implementations across multiple FPGAs to abstract hardware details from the user as well as to provide a well-known, high-level parallel programming API. In three years, TMD-MPI has evolved in a bottom-up approach to the point where it provides software and hardware middleware layers of abstraction for communications to enable the portable 978-1-4244-2826-7/08/$25.00 c 2008 IEEE interaction between embedded processors, specialized hardware computing engines and now X86 processors; all programmed under the same message passing paradigm making it a unified programming model for HPRCs.…”

Section: Introductionmentioning

confidence: 99%

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MPI as an abstraction for software-hardware interaction for HPRCs

Saldaña¹,

Patel²,

Madill

et al. 2008

2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications

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Abstract-High Performance Reconfigurable Computers (HPRCs) consist of one or more standard microprocessors tightly coupled with one or more reconfigurable FPGAs. HPRCs have been shown to provide good speedups and good cost/performance ratios, but not necessarily ease of use, leading to a slow acceptance of this technology. HPRCs introduce new design challenges, such as the lack of portability across platforms, incompatibilities with legacy code, users reluctant to change their code base, a prolonged learning curve, and the need for a system-level Hardware/Software co-design development flow. This paper presents the evolution and current work on TMD-MPI, which started as an MPI-based programming model for Multiprocessor Systems-on-Chip implemented in FPGAs, and has now evolved to include multiple X86 processors. TMD-MPI is shown to address current design challenges in HPRC usage, suggesting that the MPI standard has enough syntax and semantics to program these new types of parallel architectures. Also presented is the TMD-MPI Ecosystem, which consists of research projects and tools that are developed around TMD-MPI to further improve HPRC usability.

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Section: An Example Of Portability and Scalabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

MPI as an abstraction for software-hardware interaction for HPRCs

Saldaña¹,

Patel²,

Madill

et al. 2008

2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications

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“…This thesis focus is a profiler for the TMD [4] [5] [6], a heterogeneous multi-core multi-FPGA system designed at the University of Toronto that uses the message passing paradigm for communications. The main purpose of this profiler is to give insight into the communications occurring between nodes and the computation performed by each node.…”

Section: Motivationmentioning

confidence: 99%

“…After the application is successfully ported in software, if the task running on one of these processors is critical it may then be optimized by substituting it with a hardware engine. Because all communications are done using the TMD-MPI protocol, a special core that encapsulates the TMD-MPI functionality, the TMDMessage Passing Engine (TMD-MPE) [6], was designed so all hardware engines can send and receive messages from other nodes in full-duplex mode. This simplifies significantly the design process of a hardware engine, as the designer will not need to be concerned with the details of the protocol such as unexpected messages and packetization.…”

Section: Computation Nodesmentioning

confidence: 99%

A profiler for a heterogeneous multi-core multi-FPGA system

Nunes

Saldaña²,

Chow

2008

2008 International Conference on Field-Programmable Technology

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The TMD is a heterogeneous multi-FPGA system that uses the Message Passing Interface (MPI) programming model to build systems comprised of processors and hardware engines implemented on FPGAs, all interacting using MPI messages. This thesis implements a profiling system that can monitor communication calls and user states. The data is compatible with Jumpshot, a visualizer already used for software-based MPI applications. We demonstrate the capability of the profiler on a number of applications and show that the profiler can be used for multiple FPGAs across multiple boards.ii Acknowledgements First and foremost I would like to thank my supervisor Professor Paul Chow for his guidance and technical advice which were of highest value throughout the course of this MASc. I would also like to thank Emanuel and Alex, for their suggestions and conversations; Manuel, Arun and Chris for their expertise advice; and all the remaining group members: Andrew, Danny, David, Ali, Keith, Daniel Ly, Danyao, Richard, Tom, Mike, Nasim, and Matt for their support. Last but not the least, Professor João Cardoso who first contacted the University of Toronto and provided guidance throughout all my undergrad in Portugal.iii

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“…The use of high-level parallelism with Chip Multi-Processor (CMP) systems are a promising solution to this problem.Because of the diversity of applications it is not possible to design a CMP system, that can meet the requirements of all applications. For this reason, there is an increasing interest in the research community to employ FPGA-based systems to design flexible CMP systems [2,3,4].…”

Section: Introductionmentioning

confidence: 99%

SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips

Mahr

Lorchner

Ishebabi

et al. 2008

2008 International Conference on Reconfigurable Computing and FPGAs

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Current technologies allow designers to use several components, like processors, memories or hardware accelerators to build a multiprocessor system on-chip. In such systems, communication can be done by passing messages between components. In this paper, a flexible subset implementation of the message passing standard, called SoC-MPI, for multiprocessor systems on-chip is presented. The implementation hides the complexity of hardware from the programmer, but then uses hardware supported functions to enhance communication. Additionally, the message passing library is integrated in an architecture synthesis flow, which has the goal to create the best possible architecture from a given parallel application. Hence several communication networks (currently limited to Xilinx FPGAs) are supported by the library to enhance design flexibility. The SoC-MPI library is evaluated with several benchmarks, including the singular value decomposition.

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Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI

Cited by 18 publications

References 14 publications

MPI as an abstraction for software-hardware interaction for HPRCs

MPI as an abstraction for software-hardware interaction for HPRCs

A profiler for a heterogeneous multi-core multi-FPGA system

SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips

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