SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips

Mahr, Philipp; Lorchner, C.; Ishebabi, H.; Bobda, Christophe

doi:10.1109/reconfig.2008.27

Cited by 36 publications

(17 citation statements)

References 9 publications

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“…IBM also explored the possibility to integrate MPI on the Cell processor [33]. In the academy, a wide number of MPI libraries have been reported so far, such as rMPI [34], TDM-MPI [35], SoC-MPI [36], RAMPSoC-MPI [37] which is more focused on adaptive systems, and the work presented in [38] about MPI task migration.…”

Section: Related Workmentioning

confidence: 99%

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

Joven

Bagdia

Angiolini³

et al. 2013

IEEE Trans. Ind. Inf.

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Abstract-Reconfigurable parallel computing is required to provide high-performance embedded computing, hide hardware complexity, boost software development, and manage multiple workloads when multiple applications are running simultaneously on the emerging network-on-chip (NoC)-based multiprocessor systems-on-chip (MPSoCs) platforms. In these type of systems, the overall system performance may be affected due to congestion, and therefore parallel programming stacks must be assisted by quality-of-service (QoS) support to meet application requirements and to deal with application dynamism.In this paper, we present a hardware-software QoS-driven reconfigurable parallel computing framework, i.e., the NoC services, the runtime QoS middleware API and our ocMPI library and its tracing support which has been tailored for a distributed-shared memory ARM clustered NoC-based MPSoC platform.The experimental results show the efficiency of our software stack under a broad range of parallel kernels and benchmarks, in terms of low-latency interprocess communication, good application scalability, and most important, they demonstrate the ability to enable runtime reconfiguration to manage workloads in message-passing parallel applications.Index Terms-Networks-on-chip (NoCs), NoC-based multiprocessor systems-on-chip (MPSoC), parallel computing, quality of service (QoS), runtime reconfiguration.

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Section: Related Workmentioning

confidence: 99%

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

Joven

Bagdia

Angiolini³

et al. 2013

IEEE Trans. Ind. Inf.

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“…Although the cores of a CMP share the same memory space, it is possible to implement the message passing models on CMPs [32] by writing and reading from shared memory locations. However, for scalability purpose, CMPs with large number of cores will be organized as a mesh of tiles, each with its own cache [27].…”

Section: Platformmentioning

confidence: 99%

Energy-Aware Mappings of Series-Parallel Workflows onto Chip Multiprocessors

Benoît

Renaud-Goud

Robert

et al. 2011

2011 International Conference on Parallel Processing

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This paper studies the problem of mapping streaming applications that can be modeled by a series-parallel graph, onto a 2-dimensional tiled CMP architecture. The objective of the mapping is to minimize the energy consumption, using dynamic and voltage scaling techniques, while maintaining a given level of performance, reflected by the rate of processing the data streams. This mapping problem turns out to be NP-hard, but we identify simpler instances, whose optimal solution can be computed by a dynamic programming algorithm in polynomial time. Several heuristics are proposed to tackle the general problem, building upon the theoretical results. Finally, we assess the performance of the heuristics through comprehensive simulations using the StreamIt workflow suite and various CMP grid sizes.Key-words: series-parallel graph; DAG; mapping; multicore; CMP; energy; power; period; throughput; DVS; DVFS; complexity; simulation; streaming applications; optimization. Energy-aware mappings of series-parallel workflows onto chip multiprocessorsRésumé : Dans ce rapport de recherche, nous nous intéressons au placement d'applications de type streaming représentées sous la forme d'un graphe série-parallèle sur un processeur multi-coeur, en essayant de minimiser l'énergie consommée tout en n'excédant pas une borne sur un critère de performance, la période. La partie théorique démontre la NP-complétude ou la polynomialité du problème, selon des propriétés structurelles du multi-coeur (chaîne de coeurs, uni-ou bi-directionnelle, grille de coeurs) et la largeur du graphe de l'application (bornée ou non). Le problème le moins contraintétant NP-complet, nous décrivons dans la partie expérimentale quatre heuristiques, puis les comparons entre elles, et donnons un programme linéaire en nombres entiers qui permet d'obtenir la solution optimale en temps exponentiel.

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“…Multiple pairs of End Points) between every two processes so that the achieved aggregate bandwidth is high. [2] , gives the message passing interface library implementation of the hardware architecture of the System On Chip. In these types of high performance systems, there is highly need of the communication between components.…”

Section: Introductionmentioning

confidence: 99%

Survey: Analysis of Various Message Passing Interface Implementations

2015

IJAERD

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SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips

Cited by 36 publications

References 9 publications

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

Energy-Aware Mappings of Series-Parallel Workflows onto Chip Multiprocessors

Survey: Analysis of Various Message Passing Interface Implementations

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