Configurable Hardware Architecture of Multidimensional Convolution Coprocessor

Boonyuu, Geranun; Wisayataksin, Sumek

doi:10.1109/ica-symp50206.2021.9358447

Cited by 4 publications

(1 citation statement)

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“…Ref. [9] included parallel processing elements (PEs) for PW convolution and DW convolution, respectively, and implemented pipeline operations between convolutional layers. Refs.…”

Section: Introductionmentioning

confidence: 99%

A Configurable Accelerator for Keyword Spotting Based on Small-Footprint Temporal Efficient Neural Network

Chen

2022

Electronics

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Keyword spotting (KWS) plays a crucial role in human–machine interactions involving smart devices. In recent years, temporal convolutional networks (TCNs) have performed outstandingly with less computational complexity, in comparison with classical convolutional neural network (CNN) methods. However, it remains challenging to achieve a trade-off between a small-footprint model and high accuracy for the edge deployment of the KWS system. In this article, we propose a small-footprint model based on a modified temporal efficient neural network (TENet) and a simplified mel-frequency cepstrum coefficient (MFCC) algorithm. With the batch-norm folding and int8 quantization of the network, our model achieves the accuracy of 95.36% on Google Speech Command Dataset (GSCD) with only 18 K parameters and 461 K multiplications. Furthermore, following a hardware/model co-design approach, we propose an optimized dataflow and a configurable hardware architecture for TENet inference. The proposed accelerator implemented on Xilinx zynq 7z020 achieves an energy efficiency of 25.6 GOPS/W and reduces the runtime by 3.1× compared with state-of-the-art work.

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“…Ref. [9] included parallel processing elements (PEs) for PW convolution and DW convolution, respectively, and implemented pipeline operations between convolutional layers. Refs.…”

Section: Introductionmentioning

confidence: 99%