A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture

Gong, Wenqiang; Zhou, Fang; Ge, Fen

doi:10.1109/asicon58565.2023.10396531

2023 IEEE 15th International Conference on ASIC (ASICON) 2023

DOI: 10.1109/asicon58565.2023.10396531

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A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture

Wenqiang Gong,

Fang Zhou,

Fen Ge

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A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture

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References 10 publications

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