Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput

Cabal, Jakub; Benáček, Pavel; Kekely, Lukáš; Kekely, Michal; Pus, Viktor; Kořenek, Jan

doi:10.1145/3174243.3174250

Cited by 19 publications

(18 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recent high-performance FPGAs are shown to support a throughput of nearly 1 Tbps. 21 The FPGA is highly agile and meets most of the programmable switch ASIC requirements. However, it cannot be used for high-speed routing due to inherent limitations in realizing a large size content addressable memory.…”

Section: Pdp and P4mentioning

confidence: 99%

“…A reconfigurable packet parser that handles more than 1 Tbps is demonstrated based on an FPGA showcases the I/O processing capability of the FPGA. 21 While such capability is available, adding TCAM lookup resources to FPGA is required before positioning alternate hardware as a full-fledged network switch. Simplified I/O processing can enable the use of alternate hardware as a replacement of network switch.…”

Section: Network Use Casesmentioning

confidence: 99%

See 1 more Smart Citation

A minimal resource high‐speed routing lookup mechanism for servers with NetFPGAs

Sankaran¹,

Sivalingam

2021

Trans Emerging Tel Tech

View full text Add to dashboard Cite

This paper studies how high-performance computer servers, equipped with Field-Programmable Gate Arrays (FPGAs), can perform high-speed routing. In particular, routing table lookup is considered since it is a key packet processing bottleneck for future routers that need to operate at Petabits-per-second.The paper defines and evaluates three routing lookup schemes used by routers/switches, using Xilinx NetFPGA SUME programmable data plane hardware boards. Two existing schemes, namely IP address-based Longest Prefix Matching and Multi-Protocol Label Switching tag-based exact matching are implemented. In addition, the paper presents a new routing scheme called No Lookup Forwarding Scheme (NLFS) that does not use conventional lookup tables. The NLFS approach adds a custom routing tag that does not require any form of (forwarding) table lookup, and independent of the Binary/Ternary Content Associate Memory (CAM) capacity in the switch/router. The experimental results show that the NLFS scheme utilizes less FPGA resources, while reducing packet lookup latency by up to 18% against longest prefix match which is the de facto lookup mechanism used in switches. The key contribution of this work is that it enables the use of NetFPGAs to reduce CAM capacity requirements in switches/routers to help reduce memory costs. The proposed scheme has several use cases, including provision of on-demand increase of packet routing capacity in data center networks and support for Network Function Virtualization-based systems.

show abstract

Section: Pdp and P4mentioning

confidence: 99%

Section: Network Use Casesmentioning

confidence: 99%

A minimal resource high‐speed routing lookup mechanism for servers with NetFPGAs

Sankaran¹,

Sivalingam

2021

Trans Emerging Tel Tech

View full text Add to dashboard Cite

show abstract

“…A new parser architecture is presented by Jakub et al in [21], which is capable to currently scale up to a terabit throughput in a Xilinx UltraScale+ FPGA, and the overall processing speed is sustained even on the shortest frame lengths. Its main method is building a protocol process module pool, and multiple packets are processed in parallel in this pool.…”

Section: Packet Parser Solutionsmentioning

confidence: 99%

A Fast Approach for Generating Efficient Parsers on FPGAs

Cao

Zhang

et al. 2019

Symmetry

View full text Add to dashboard Cite

The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets—this is the precondition for further processing and finally forwarding these packets. This paper presents a framework designed to transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays (FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler. The hardware architecture comprises many components with varying functionality, each of which has its own optimized VHDL template. By using the output of a standard frontend P4 compiler, our proposed compiler extracts the parameters and relationships from within the used components, which can then be mapped to corresponding templates by configuring, optimizing, and instantiating them. Finally, these templates are connected to output VHDL code. When a prototype of this framework is implemented and evaluated, the results demonstrate that the throughputs of the generated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with state-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when similar amounts of resources are being used.

show abstract

“…There are countless papers in which FPGA-based parsers are proposed. [9], [10], [11], [12] and [13] are just a few examples of such research efforts which achieve throughput on the scale of hundreds of Gigabits per second. However, it should be noted that these architectures achieve this throughput by means of operating on ultra-wide input due to their low frequencies.…”

Section: Introductionmentioning

confidence: 99%