2008
DOI: 10.1002/cta.509
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Configurable 3D‐integrated focal‐plane cellular sensor–processor array architecture

Abstract: SUMMARYMixed-signal cellular visual microprocessor architecture with digital processors is described. An Application Specific Integrated Circuit (ASIC) implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face-to-face-type integration, and one or several cascaded array of mainly identical (single instruction multiple data, SIMD) processing elements. The individual array elements were derived from the same general Hardware Description Langu… Show more

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Cited by 27 publications
(18 citation statements)
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“…Each processor, very simple, can also include an image sensor to eliminate the IO bottleneck. Some representative examples are (Foldesy et al, 2008;Garrido et al, 2008;Lopich & Dudek, 2008). There are also approaches closer to the biological vision, as (Koyanagi et al, 2001) or (Constandinou et al, 2004).…”
Section: Application-specific Integrated Circuitsmentioning
confidence: 99%
“…Each processor, very simple, can also include an image sensor to eliminate the IO bottleneck. Some representative examples are (Foldesy et al, 2008;Garrido et al, 2008;Lopich & Dudek, 2008). There are also approaches closer to the biological vision, as (Koyanagi et al, 2001) or (Constandinou et al, 2004).…”
Section: Application-specific Integrated Circuitsmentioning
confidence: 99%
“…As can be seen in Figure 3, Xenon chip [25] is constructed of an 8×8, locally interconnected cell arrangement. Each cell contains a sub-array of 8×8 photosensors; an analog multiplexer; an 8 bit AD converter; an 8 bit processor with 512 bytes of memory; and a communication unit of local and global connections.…”
Section: Coarse-grain Cellular Parallel Architecturesmentioning
confidence: 99%
“…Pipe-line architecture (CASTLE [24][23], Falcon [16], C-MVA [21]) 3. Coarse-grain cellular parallel architecture (Xenon [25]); 4. Fine-grain fully parallel cellular architecture with discrete time processing (SCAMP [15], Q-Eye [19]); 5.…”
Section: Introductionmentioning
confidence: 99%
“…This 8x8 digital processor array ( Fig. 8) is an advanced version of our previous deign [16]. The distinguishing feature of this new implementation is the increased memory size and higher flexibility in the processed window size and distribution.…”
Section: Foveal Processor Arraymentioning
confidence: 99%