Towards the Optimal Hardware Architecture for Computer Vision

Nieto, Alejandro; Vilariño, D.L.; Sánchez, Víctor Brea

doi:10.5772/34023

Cited by 6 publications

(4 citation statements)

References 106 publications

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“…Feature detection and description operations are usually performed on standard microprocessors or, less frequently, on graphics processing units. Although such hardware platforms are affordable and well established, they are not best suited for power- and size-constrained applications [27, 28]. On the other hand, the embedded and mobile microprocessors designed for use in such conditions have a limited computational throughput.…”

Section: Related Workmentioning

confidence: 99%

A High-Performance FPGA-Based Image Feature Detector and Matcher Based on the FAST and BRIEF Algorithms

Fularz

Kraft

Schmidt

et al. 2015

International Journal of Advanced Robotic Systems

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Image feature detection and matching is a fundamental operation in image processing. As the detected and matched features are used as input data for high-level computer vision algorithms, the matching accuracy directly influences the quality of the results of the whole computer vision system. Moreover, as the algorithms are frequently used as a part of a real-time processing pipeline, the speed at which the input image data are handled is also a concern. The paper proposes an embedded system architecture for feature detection and matching. The architecture implements the FAST feature detector and the BRIEF feature descriptor and is capable of establishing key point correspondences in the input image data stream coming from either an external sensor or memory at a speed of hundreds of frames per second, so that it can cope with most demanding applications. Moreover, the proposed design is highly flexible and configurable, and facilitates the trade-off between the processing speed and programmable logic resource utilization. All the designed hardware blocks are designed to use standard, widely adopted hardware interfaces based on the AMBA AXI4 interface protocol and are connected using an underlying direct memory access (DMA) architecture, enabling bottleneckfree inter-component data transfers.

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Section: Related Workmentioning

confidence: 99%

A High-Performance FPGA-Based Image Feature Detector and Matcher Based on the FAST and BRIEF Algorithms

Fularz

Kraft

Schmidt

et al. 2015

International Journal of Advanced Robotic Systems

View full text Add to dashboard Cite

show abstract

“…Before beginning the design process of a new architecture, it is essential to analyze the operations and data flow of the algorithms we want to address. In [3], a review of the computing paradigms present in the most relevant algorithms employed in Computer Vision and the revision of state of the art hardware implementations on a wide range of desktop and embedded devices was performed. These analysis lead us to divide the mathematical operations of the Computer Vision algorithms into three groups:…”

Section: Previous Workmentioning

confidence: 99%

“…In addition, some representative algorithms were implemented on different devices, a massive parallel SIMD processor (SCAMP-3 Vision System), a pure streaming computing solution (Ambric Am2045) and an FPGA-based coarsegrain SIMD unit. Part of this work can be found in [3] [6]. Besides dedicated platforms, extensible processors were also examined.…”

Section: Previous Workmentioning

confidence: 99%

SIMD/MIMD Dynamically-Reconfigurable Architecture for High-Performance Embedded Vision Systems

Nieto

Vilariño

Brea

2012

2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors

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Image and video processing algorithms are becoming more and more sophisticated. An efficient hardware architecture is a requirement in order to address effectively the increasing computational workload. In a context of high performance, low cost and rapid prototyping, a hybrid SIMD/MIMD architecture for image processing is proposed in this work. By reusing functional units and including a dynamically reconfigurable datapath, this architecture enables high performance devices for general image processing tasks with high application development productivity when using as part of a System-on-Chip. A 32-bit 128-unit coprocessor was prototyped on a Virtex-6 FPGA and results show a peak performance of 19.6 GOP/s.

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“…Compared to conventional image processing, this novel camera technique offers two major advantages: Firstly, image preprocessing on the camera chip reduces data transfer between camera and processor which forms a common bottleneck in conventional image processing systems. Secondly, SIMD processors are in particular efficient in terms of computational speed and power consumption for low level image processing operations [10]. This paper discusses the properties of CNN-cameras for surface inspection applications at the example of the wire drawing application.…”

Section: Introductionmentioning

confidence: 99%

Inspecting rapidly moving surfaces for small defects using CNN cameras

Blug

Carl

Höfler

2013

Videometrics, Range Imaging, and Applications XII; And Automated Visual Inspection

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A continuous increase in production speed and manufacturing precision raises a demand for the automated detection of small image features on rapidly moving surfaces. An example are wire drawing processes where kilometers of cylindrical metal surfaces moving with 10 m/s have to be inspected for defects such as scratches, dents, grooves, or chatter marks with a lateral size of 100 µm in real time. Up to now, complex eddy current systems are used for quality control instead of line cameras, because the ratio between lateral feature size and surface speed is limited by the data transport between camera and computer. This bottleneck is avoided by cellular neural network (CNN) cameras which enable image processing directly on the camera chip. This article reports results achieved with a d emonstrator based on this novel analogue camera computer system. The results show that computational speed and accuracy of the analogue computer system are sufficient to detect and discriminate the different types of defects. Area images with 176 x 144 pixels are acquired and evaluated in real time with frame rates of 4 to 10 kHz depending on the number of defects to be detected. These frame rates correspond to equivalent line rates on line cameras between 360 and 880 kHz, a number far beyond the available features. Using the relation between lateral feature size and surface speed as a figure of merit, the CNN based system outperforms conventional image processing systems by an order of magnitude

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Towards the Optimal Hardware Architecture for Computer Vision

Cited by 6 publications

References 106 publications

A High-Performance FPGA-Based Image Feature Detector and Matcher Based on the FAST and BRIEF Algorithms

A High-Performance FPGA-Based Image Feature Detector and Matcher Based on the FAST and BRIEF Algorithms

SIMD/MIMD Dynamically-Reconfigurable Architecture for High-Performance Embedded Vision Systems

Inspecting rapidly moving surfaces for small defects using CNN cameras

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