This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. Onchip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-m single-poly double-metal technology and features 2-s operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations. Index Terms-Analog array processors, cellular neural networks, focal plane processors, vision chips. I. INTRODUCTION C ONVENTIONAL image-processing systems use a charge-coupled device (CCD) camera for parallel acquisition of the input image and serial transmission of the digitalized image to a separate processing element. It results in huge data rates which conventional computers are not capable of analyzing in real-time. For instance, a color 512 512 pixel camera delivers about 20 MB/s, for Manuscript
This introductory chapter describes the zoo of the basic focal-plane sensor-processor array architectures. The typical sensor-processor arrangements are shown, the typical operators are listed in separate groups, and the processor structures are analyzed. The chapter gives a compass to the reader to navigate among the different chip implementations, designs, and applications when reading the book.
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