Conduction Mechanism Analysis of Inversion Current in MOS Tunnel Diodes

Abstract

Self inversion issue and excess capacitance phenomenon were observed for the first time in relatively thick silicon dioxide (SiO 2) in the form of MOS (metal(Al)/SiO 2 /p type crystalline silicon) structure. Both phenomena were based on minority carriers (electrons in this case) and studied through DC current-applied bias voltage (I-V) and AC admittance measurements in dark/light condition as a function of ambient temperature (295-380 K). Either of the cases was the departure of traditional MOS analysis, manifesting themselves in the inversion regime of MOS diode. Increase in frequency/temperature/light intensity within dark and light conditions led to weaken the maxima of hump in C-V curves and finally turned into deep depletion mode after exceeding threshold value of frequency/temperature/light intensity. In resumed conditions, supplementary I-V measurements were carried out to describe the generation and conduction mechanism(s) for minority carriers (electrons).

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

“…Clearly, the sheet resistance of the new floating gates was higher than that of the control split, (i.e., about 1.7 times for the pn-type floating gates and 2.1 times for the np-type floating gates), which was plausibly caused by the formation of a depletion zone and the narrowed channels for current flow. When a forward bias was applied to the np-type floating gate, or a reverse bias was applied to the pn-type floating gate, a depletion zone of carriers would be formed at the n-p or p-n junction interface [ 28 , 29 , 30 , 31 , 32 ], leading to an open circuit at the bottom region of the floating gates. Current flow was therefore allowed only through the top p + or n + polysilicon paths, respectively, and the narrowed channel would thus result in increased resistance, particularly for the np-type floating gates, as the mobility of holes in the p + polysilicon path was lower than that of electrons in the n + polysilicon path [ 29 , 30 ].…”

“…In comparison, for the pn-type polysilicon floating gate ( Figure 3 b) and the np-type polysilicon floating gate ( Figure 3 c) at a thermal equilibrium state, the Fermi level (E f ) is close to the valence band in the p + region (conduction by holes) and close to the conduction band in the n + region (conduction by electrons). At a constant Fermi level, the distributions of carriers as well as the energy levels of the conduction band (E c ) and valence band (E v ) are thus different in the p + and n + regions at the neutral state, and a depletion zone (a thin region with very few carriers) of high electrical resistance will accordingly be formed at the p-n or n-p junction interface [ 29 , 30 , 31 , 32 ].…”