Concentrator Access Networks for Programmable Logic Cores on SoCs

Abstract

-The inclusion of programmable logic cores in modern SoCs motivates the need for an access network to make full use of this resource. The programmable nature of these cores removes the requirement of input/output ordering on this access network. Theoretical work on a class of unordered networks called concentrators has shown that as these networks become large, they have a lower cost than ordered or permutation networks. However, currently known constructions of concentrator networks are not lower cost than permutation networks for the entire range of networks of the size required for SoCs. This paper demonstrates the differences in the cost and depth of concentrator and permutation networks. It will also present a new construction of a concentrator network that has lower cost and depth than a permutation network for all configurations.

Interconnection fabric design for tracing signals in post-silicon validation

“…Recently, Quinton and Wilton [17] proposed to use the Narasimha concentrator to connect a programmable logic block to the other cores in SoC designs. While the original Narasimha concentrator requires the number of inputs to be 2 k (similar to the Clos network), it can be easily revised to take arbitrary number of inputs, as shown in Fig.…”

“…[17] also did minor modifications to the Narasimha concentrator design to further reduce its hardware cost. To be specific, [17] proposed to replace the last crossbar unit with two direct wires at the input stage, as shown in Fig. 4.…”

“…Starting from the revised Narasimha concentrator that is able to take arbitrary number of inputs as shown in [17] (without using their simplification method as it violates our desired concentration capability, see Section 2.2), we propose several simplification rules to reduce the DfD cost of the concentration network, detailed in the following.…”

BackSpace: Formal Analysis for Post-Silicon Debug

“…We rely on prior work on access mechanisms to observe on-chip signals. In this paper, we consider one efficient, flexible, and reconfigurable architecture that provides this access [15]. Abramovici et al [1] propose a different reconfigurable architecture, also with the goal of providing efficient signal access for debugging.…”

“…If the set of N mon signals cannot be determined at fabrication time, the selection of these signals can be made programmable at debug-time using a concentrator network [15]. Such a network would programmably connect a subset of the N mon monitored signals for use in the signature.…”