Comprehensive understanding of hot carrier degradation in multiple-fin SOI FinFETs

Impact of Hot Carrier Aging on the Performance of Triple-Gate Junctionless MOSFETs

“…Thus, in the TG JL transistor with L = 95 nm interface damage dominates the whole degradation, rather than HC injection into the gate oxide bulk defects. This result is different from that found in IM channel FinFETs, where the main degradation mechanism is the HC injection into the gate oxide bulk defects [18]. This differentiation may be due to the bulk conduction in JL transistors instead of the surface conduction in IM transistors.…”

“…As the stress proceeds further, above 50 s the interface states density increases tending to saturation. Similar behavior of the interface trap density with stress time has been observed in short channel IM FinFETs [18], [19]. Following the energydriven HC model for single particle or multiple particle Si-H bond breaking process [20] and accounting for saturation of the degradation, in the stress time region above 50 s the interface states generation can be modeled by the relationship [10]:…”

“…In order to clarify the origin of the degradation mechanisms of the macroscopic transistor parameters, we considered the microscopic transistor parameters, such as interface trap (D it ) and oxide trap (N ox ) densities. The change of the threshold voltage V t with stress time can be correlated with the change of the interface trap density D it and/or the change of the oxide trap density N ox by the relationship [18]:…”

“…For assessing the relative importance of the negative charge from interface states, considering uniform energy distribution of the interface states, the HCgenerated interface trap density was extracted from the subthreshold swing change SS using the relation D it = SSC ox E/qkTln (10). The dependence of the HC-induced interface states concentration D it with stress time, extracted from the subthreshold slope change [18], is presented in Fig. 4(b) for the TG JL MOSFET with channel length L = 95 nm.…”

An Investigation of DC/AC hot carrier degradation in multiple-fin SOI FinFETs

“…For the device with NFin=6, the n is 0.41 that is close to the power law factor (n=0.5) in conventional large scale device under its most degrading stress condition (Vgs=0.5Vds), whose HCD mechanism is dominated by the interface charge (Nit). As our previous work [11] reported that the small n under HCD stress condition indicates that the degradation mechanism is large percentage dominated by oxide traps (N ot). Therefore, Fig.…”