Impact of Hot Carrier Aging on the Performance of Triple-Gate Junctionless MOSFETs

Abstract

In this work, we investigate the impact of the hot carrier (HC) aging on the performance of nanoscale n-channel triple-gate junctionless MOSFETs with channel length varying from 95 down to 25 nm. The devices were electrically stressed in the on-state region of operation at fixed gate voltage V g = 1.8 V and drain bias V d varying from 0.8 to 1.8 V, with the stress time being a variable parameter. The device degradation was monitored through the relative change with stress time of the threshold voltage, the subthreshold swing, the linear drain current and the gate current. We demonstrate that the HC degradation is exclusively due to the interface state generation when the stress voltage V d is as high as V g , following the energy driven HC model. For bias stress conditions with V d /V g  1 the threshold voltage and the subthreshold slope remain unchanged, whereas the on-state drain current is degraded, attributed to HCinduced damage restricted in the drain contact.

Compensation of Hot Carrier Degradation Enabled by Forward Back Bias in π-GAA-π MOSFET

“…As can be seen from Figs. 6(a) and 6(b), the similar electron energy near the drain side for both devices (dashed circle) agrees with the normal view that localized damages happen at the drain side where carriers obtain enough energy for injection [22], [23]. While since the bottom surface of GAA gate is far away from the drain side, the carrier energy there is maintained at a relatively low level (dotted circle).…”

Synergic Effect of Misaligned Gate and Temperature on Hetero‐Dielectric Double‐Gate Junctionless Metal–Oxide‐Semiconductor Field‐Effect Transistors for High‐Frequency Application

“…[20] This makes double-gate junctionless MOSFETs particularly attractive for applications requiring high performance, low-power consumption, and improved scaling. [21,22] Moreover, double-gate junctionless MOSFETs exhibit improved immunity to process variations, making them a potential solution for future technology nodes. [23] However, the implementation of double-gate junctionless MOSFETs presents its own set of challenges.…”