Comprehensive investigations on charge diffusion physics in SiN-based 3D NAND flash memory through systematical Ab initio calculations

Wu, Jixuan; Han, Dan; Yang, Wenjing; Chen, Shiyou; Jiang, Xiangwei; Chen, Jiezhi

doi:10.1109/iedm.2017.8268327

Cited by 22 publications

(13 citation statements)

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“…As aforementioned, P/E stress impacts on shallow traps generation is a critical concern in 3D NAND reliabilities. P/E stress can break the hydrogen bonding at the interface and in the bulk Si 3 N 4 , as we clarified in [21].…”

Section: Resultsmentioning

confidence: 79%

“…Stability and conversion between them are discussed. Considering our previous calculation results [21] that the nitrogen vacancy (V N ) defect has the lowest formation energy, the H substitute N (H N ) defect has the similar trap level with the experimental results, and the O atom cause shallow traps, we focus on the defects of V N , H N , and O incorporation in this work. All of the following atom structures are relaxed at the neutral state or after the electron/hole (e − /h + ) injection-removal cycle (I-R), as shown in Fig.…”

Section: Figure 3 the Final Structure Of Defects Combined The Free Hmentioning

confidence: 98%

“…As for O incorporated defect that exists nearby the SiO x /Si 3 N 4 interface, it is known that the interstitial O atom (V N +O i defect) performs as the shallow electron trap center and O atom substituted N atom (O N defect) performs as the hole trap center [21]. In this work, the free H combination together with electron/hole injection is investigated.…”

Section: Figure 3 the Final Structure Of Defects Combined The Free Hmentioning

confidence: 99%

“…This was explained by the degradation of lateral charge diffusion from shallow traps generation under repeated P/E stress. In our previous study on the relationship of shallow traps and the lateral charge diffusion [21], it was found that the oxygen (O) in Si 3 N 4 nearby the SiO 2 /Si 3 N 4 interface could form shallow traps and cause lateral charge diffusion. It has also been reported in [22]- [24] that the O-related defects could cause the collapse of a Si 3 N 4 layer.…”

Section: Introductionmentioning

confidence: 99%

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Atomistic Study of Lateral Charge Diffusion Degradation During Program/Erase Cycling in 3-D NAND Flash Memory

Chen

Jiang

2019

IEEE J. Electron Devices Soc.

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Impacts of lateral charge diffusion on the retention characteristics of charge-trapping (CT) 3-D NAND flash memory are comprehensively studied in this paper. Atomistic study through ab initio calculation is carried out to understand the correlations between P/E stress induced shallow trap generations and pre-existing traps in Si 3 N 4. It is shown that more shallow traps will be generated with a combination of electron/hole injections and free hydrogen (H) during P/E cycling. Our results strongly suggest that process optimizations to control free H in Si 3 N 4 CT layer could be a key point for robust retention characteristics. INDEX TERMS Silicon nitride, 3D NAND, charge trapping, lateral charge diffusion, shallow trap.

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Section: Resultsmentioning

confidence: 79%

Section: Figure 3 the Final Structure Of Defects Combined The Free Hmentioning

confidence: 98%

Section: Figure 3 the Final Structure Of Defects Combined The Free Hmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Atomistic Study of Lateral Charge Diffusion Degradation During Program/Erase Cycling in 3-D NAND Flash Memory

Chen

Jiang

2019

IEEE J. Electron Devices Soc.

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“…Here, Si3N4 serves as a CT layer in 3D NAND flash memory, in which the electron trap centers are VN-H and SiN-H defects. [40] While electrons could be trapped in the shallow-trap centers (VN and VN-O) of Si3N4, these trapped electrons are able to escape from the CT layer due to the PF emission. The escaped electrons could be trapped again by VO-H in SiO2, leading to vertical charge loss.…”

Section: B Defects-induced Vertical Charge Lossmentioning

confidence: 99%

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

Wang

et al. 2021

IEEE Access

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In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss. Here, by first-principles calculations, we present a detailed study on the defects in the transition layer Si2N2O to comprehend their impacts on charge loss in CT 3D NAND flash memory. It is shown that shallow-trap centers, such as intrinsic nitrogen vacancy (VN) and interstitial Ti (Tii), can couple with the conduction band of Si2N2O to lead to lateral charge loss. On the other hand, the N substituting Si atom (NSi) and Ti substituting Si atom (TiSi) defects in the transition layer can couple through resonance with the trap centers in Si3N4, leading to vertical charge loss from the CT layer to the transition layer. Our results strongly suggest that appropriate treatment of the transition layer and hydrogen passivation are both important for avoiding charge loss in CT 3D NAND flash memory.

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Computational Associative Memory with Amorphous Metal‐Oxide Channel 3D NAND‐Compatible Floating‐Gate Transistors

Sun

Samanta

et al. 2022

Adv Elect Materials

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3D NAND has been enabling continuous NAND density and cost scaling beyond conventional 2D NAND since sub‐20‐nm nodes. However, its poly‐Si channel suffers from low mobility, instability caused by grain boundaries, and large device‐to‐device variations in electrical characteristics at highly scaled device dimensions. These drawbacks can be overcome by introducing an amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) channel, which has the advantages of ultralow OFF current, back‐end‐of‐line compatibility, higher mobility than poly‐Si, and free of grain boundaries due to the amorphous nature. In this work, ultrascaled floating‐gate (FG) transistors with a channel length down to 60 nm are reported, achieving the highest ON current of 127 µA µm−1 among all reported a‐IGZO‐based flash devices for high‐density, low‐power, and high‐performance 3D NAND applications. Furthermore, a nonvolatile and area‐efficient ternary content‐addressable memory (TCAM) with only two parallel‐connected a‐IGZO FG transistors is experimentally demonstrated to address the TCAM scalability issue. Experimentally calibrated array‐level simulations show that this design achieves at least a 240 × array‐size scalability and a 2.7‐fold reduction in search energy than TCAMs based on complementary metal‐oxide‐semiconductor technology using 16 transistors, two‐transistor‐two‐resistive random access memory, and two‐ferroelectric field‐effect‐transistor.

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Comprehensive investigations on charge diffusion physics in SiN-based 3D NAND flash memory through systematical Ab initio calculations

Cited by 22 publications

References 1 publication

Atomistic Study of Lateral Charge Diffusion Degradation During Program/Erase Cycling in 3-D NAND Flash Memory

Atomistic Study of Lateral Charge Diffusion Degradation During Program/Erase Cycling in 3-D NAND Flash Memory

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

Computational Associative Memory with Amorphous Metal‐Oxide Channel 3D NAND‐Compatible Floating‐Gate Transistors

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