Comprehensive Evaluation and Study of Pattern Dependency Behavior in Selective Epitaxial Growth of B-Doped SiGe Layers

Kolahdouz, Mohammadreza; Hållstedt, Julius; Khatibi, Ali; Östling, Mikael; Wise, R.; Riley, D. Jason; Radamson, Henry H.

doi:10.1109/tnano.2008.2009219

Cited by 27 publications

(25 citation statements)

References 10 publications

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“…It is worth mentioning here that the strain relaxation of thin strained layers may occur through roughness (or unevenness) of the layers and not creating the misfit dislocation. 27,28 In this case, one may conclude that the noise behavior is sensitive to the strain fluctuation within the layers. This could generate scatting of carriers during the transport through the multilayers.…”

Section: Resultsmentioning

confidence: 94%

Sensitivity of Signal-to-Noise Ratio to the Layer Profile and Crystal Quality of SiGe/Si Multilayers

Radamson

Moeen

Abedin

et al. 2016

ECS J. Solid State Sci. Technol.

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This study presents signal-to-noise ratio (SNR) measurements of single crystalline dots or layers of SiGe/Si in multilayer structures in terms of Ge content, interfacial and layer quality. All multilayers were processed in form of mesas and the noise behavior of electrical signal was investigated by comparing the power spectral density curves and K 1/f values. The SiGe/Si multilayer structures were also characterized by the conventional material analysis tools and the results were compared to the noise measurements. The quality of SiGe/Si interface or SiGe layer was monitored by intentional exposure to oxygen in range of 2-1600 nTorr either during or prior to SiGe growth. The results demonstrated that SNR was sensitive to the interfacial and layer quality, and the Ge content in a multilayer structure. SiGe alloys have been widely integrated in large variety of devices such as CMOS for strain engineering, 1-3 bipolar transistors, 4,5 photonic detectors, 6 bolometers, 7-9 quantum cascade lasers 10 and bio-or gas-sensors.11-13 For these applications, SiGe material is grown at low temperatures (350-650• C) where the quality of layers and interfaces plays a critical role in device characteristics. Since high strain amount is often sought then layers with high Ge content have to be grown below the critical thickness in the metastable region. One problem with epi-layers grown at low temperatures is oxygen and moisture contamination which is rooted from epitaxy environment and the purity of the reactant gases. 14,15 An important criterion in all types of devices is the signal-tonoise ratio (SNR) which indicates the quality of the electrical signal. Noise measurement is a sensitive method which can provide accurate information about any minor defects in the crystal.In this article, SiGe material is grown at low temperatures and integrated in a multilayer structure with Si barriers (e.g. SiGe/Si) where the number of periodicity, layer and interface quality were studied by noise measurements. The SiGe material was either in form of two-dimensional layer or dots. Furthermore, the integrity of epitaxial growth at low temperatures in terms of oxygen contamination was presented. A discussion of how sensitive the conventional characterization tools are compared to noise measurements for detection of defects has also been included. ExperimentalThe SiGe/Si multilayer structures were deposited on Si(100) substrates in temperature range of 350-650• C at 20 torr using reduced pressure chemical vapor deposition (RPCVD). The reactant gases for SiGe growth were GeH 4 or Ge 2 H 6 and SiH 4 or Si 2 H 6 as Ge and Si sources, respectively. All SiGe layers were grown below the critical thickness according to the published data.15-17 The quality of epi-layers and SiGe/Si interface could be monitored by exposing to oxygen during epitaxy or at the interfaces. For these experiments, the oxygen partial pressure was in range of 2-1600 nTorr. In order to determine the flux and absorption of oxygen in the reactor a residual gas analyzer (RGA) was c...

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Section: Resultsmentioning

confidence: 94%

Sensitivity of Signal-to-Noise Ratio to the Layer Profile and Crystal Quality of SiGe/Si Multilayers

Radamson

Moeen

Abedin

et al. 2016

ECS J. Solid State Sci. Technol.

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“…The 3D architecture was designed and manufactured for 22 nm node. SiGe The epi-layers may suffer from several problems e.g., facet formation [44,45], defects, micro/loading, non-uniform strain distribution, surface roughness and pattern dependency effect [46][47][48][49][50]. The pattern dependency happens when the density and size of the transistor vary in a chip.…”

Section: Stress Engineeringmentioning

confidence: 99%

“…This problem can be decreased by optimizing the growth parameters (high HCl partial pressure, low total pressure and high hydrogen carrier gas pressure) and by designing chip layouts where the exposed Si is uniformly distributed over the chip's area to create uniform gas consumption [50]. The epi-layers may suffer from several problems e.g., facet formation [44,45], defects, micro/loading, non-uniform strain distribution, surface roughness and pattern dependency effect [46][47][48][49][50]. The pattern dependency happens when the density and size of the transistor vary in a chip.…”

Section: Stress Engineeringmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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“…Although selective epitaxy is very attractive deposition technique for MOSFETs but issues e.g. facet formation [11], non-uniformity of layer profile inside the oxide openings (micro-loading) or over different parts of a chip or wafer (global loading or pattern dependency) are inherited [12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

“…Strong efforts were spent to find out methods to improve the nonuniform growth, but eliminating this effect is still a challenge [12][13][14][15][16][17][18]. Some of these works show that the pattern dependency can be decreased (\5 %) [18], but so far there is no remedy to totally eliminate this problem.…”

Section: Introductionmentioning

confidence: 99%