Compliant Wafer Level Package for Enhanced Reliability

Abstract

Wafer Level Package (WLP) volumes are steadily increasing due to their small package size and low manufacturing cost. However, applications to date have been mostly limited to die smaller than 5mm x 5mm. Solder joint fatigue due to stresses generated by the CTE mismatch between the die and the printed circuit board (PCB) limits adoption of WLP for large dies.Tessera's new compliant WLP technology greatly enhances thermal fatigue reliability of the package. A compliant layer under the solder joints effectively dissipates thermomechanical stress between the die and the PCB. FEA analysis was carried out to optimize compliant layer shape and mechanical properties, several materials were evaluated for this application, and prototype units were built. The prototype 9mm x 14mm packages exceeded 1600 cycles of temperature cycling from -40 o C to 125 o C. A compliant WLP package version with copper pins was also developed and tested for continuity at the wafer level. This structure has the potential to reduce wafer level test and burn-in (WLBT) costs substantially by eliminating the need for expensive die contact on the whole wafer contactor. IntroductionChip scale packages (CSPs) are widely used for electronic packages that require small form factor and high frequency performance. One example is a dynamic random access memory (DRAM). In the past, DRAMs were primarily packaged in small outline packages (TSOPs). However, the increased performance requirements of DDR2 DRAM could not be met with TSOPs. Consequently, CSPs have become the new standard.For many small die size components such as logic and analog ICs, WLP is a lower cost packaging solution than CSP due to elimination of packaging substrate, high parallelism in package processing and minimization of component handling. WLP also gives the smallest possible package form factor. However, the current reliable die size limit for a nonunderfilled WLP is about 5mm x 5mm. The limiting factor is thermal fatigue reliability. The coefficient of thermal expansion (CTE) for silicon is approximately 3 ppm/ o C while CTE for printed circuit board (PCB) is 14-18 ppm/ o C. As the package size increases, the stress generated by the large CTE mismatch between the die and the PCB causes the solder joint to crack and fracture. Some reliability improvement can be achieved by means of constraining the solder joint with a preapplied underfill 1 . However, the effect is limited and the approach increases cost. CSP packages face the same fundamental reliability challenge. The solution is the µBGA family of CSPs

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

“…The ideal process for a compliant interconnect would have only batch fabrication steps, few masks, no expensive materials, conventional processing tools, and thus low costs. Solutions proposed for this application include compliant layers under the solder [8], metallization formed over organic elastomers [9], [10], springs formed from wirebonds [11], and helical springs formed by electroplating through multiple layers of photoresist [12]. The wire-bond approach is the most commercially mature spring, but due to its serial manufacturing process, is inherently more expensive than a batch process.…”

Board level temperature cycling study of large array Wafer Level Package

“…Kazama et al [13] employed the finite element analysis (FEA) to optimize the built-in stressrelaxation layer for reducing the strain of the solder bumps. Gao et al [14] reported a novel design to enhance the board level reliability by incorporating a compliant polymer layer under the UBM.…”

Reliability enhancement of wafer level packages with nano-column-like hollow solder ball structures

“…Standard WLP, which is similar to a typical flip chip technology, has evolved with the incorporation of redistribution layer (RDL) process [5][6][7][8], copper post process [9], and compliant layer process [10]. These WLP structures have demonstrated the significant enhancement and improvement on solder joint reliability.…”

“…Polymer film layer, in which redistribution traces are embedded, serve as a stress buffer layer to reduce the stress level in solder joints. It is generally conceived that the high compliance of polymer film (e.g., low Young's modulus) results in solder joint stress reduction [10]. Ball shape, geometry, standoff height, and material also play an important role in thermo-mechanical performance of WLPs [11][12][13][14][15][16].…”