Comparisons of Design and Yield for Large-Area 10-kV 4H-SiC DMOSFETs

Howell, Robert S.; Buchoff, S.; Campen, S. Van; McNutt, Ty; Hearne, Harold; Ezis, A.; Sherwin, M.E.; Clarke, R.C.; Singh, Ranbir

doi:10.1109/ted.2008.926684

Cited by 12 publications

(4 citation statements)

References 6 publications

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“…A device size that is too large will result in low yields due to material and process defects and so an optimal device area must be determined. Based on defect distribution calculations [3], a diode active area of 0.09 cm 2 (0.17 cm 2 total area) was chosen as the optimal size for maximizing area and yield. Subsequently, PiN diodes were designed and fabricated on three-inch 4H-SiC n+ substrates with a 20 µm epitaxial n-drift layer doped to 5 x 10 14 cm -3 .…”

Section: Wafer-scale Interconnectionmentioning

confidence: 99%

11.72 cm<sup>2</sup> SiC Wafer-Scale Interconnected 1.8 kV / 64 kA PiN Diode

Snook

Hearne

McNutt

et al. 2012

MSF

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To meet the large current handling requirements of modern power conditioning systems, paralleling of a large number of devices is required. This increases cost and complexity through dicing, soldering, and forming multiple wire bonds. Furthermore, paralleling discrete devices increases package volume/weight and reduces power density. To overcome these complexities, PiN diodes were designed, fabricated at high yields, tested, and interconnected on a three-inch 4H-SiC wafer to form an 11.72 cm2 wafer-scale diode. The wafer-scale diode exhibited a breakdown voltage of 1790 V at an extremely low leakage current density of less than 0.002 mA/cm2. Under pulsed conditions, the peak current through the wafer-scale diode is 64.3 kA with a forward voltage drop of 10.3 V. The dissipated energy was 382 J and the action exceeded 1.7 MA2-sec.

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Section: Wafer-scale Interconnectionmentioning

confidence: 99%

11.72 cm<sup>2</sup> SiC Wafer-Scale Interconnected 1.8 kV / 64 kA PiN Diode

Snook

Hearne

McNutt

et al. 2012

MSF

Self Cite

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“…was used to prevent excessive ringing. As shown in Figs 15. and 16, the turn-off and turn-on switching speeds were 125 kV μs −1 and 90 kV μs −1 , respectively.…”

mentioning

confidence: 91%

“…6) Many reports are available on edge termination structures that ensure breakdown voltages of over 10 kV in SiC devices. [7][8][9] SiC MOSFETs with voltage ratings exceeding 10 kV have been achieved, [10][11][12][13][14][15] including a SiC MOSFET with a specific onresistance (R on,sp ) of 204 mΩ cm 2 and a blocking voltage of 16 kV. 14) A 10 kV SiC-MOSFET with a large die size of 1 cm 2 was also developed.…”

Section: Introductionmentioning

confidence: 99%

“…14) A 10 kV SiC-MOSFET with a large die size of 1 cm 2 was also developed. 15) However, junction field-effect transistor (JFET) regions that are formed on slightly doped n − drift regions and n − drift regions with low doping concentrations at the 10 14 -cm −3 level cause high on-resistance. Although, some SiC MOSFETs have the low R on,sp and the high blocking voltage, 12,14) a SiC MOSFET with large JFET width and high doner concentration in the JFET region causes increases in the electric field of gate oxide (Eox) above the JFET region to reduce the resistance in the JFET region.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A superior 15 kV SiC MOSFET with current spreading layer for high-frequency applications

Kitai¹,

Yamaguchi²,

Hozumi³

et al. 2019

Jpn. J. Appl. Phys.

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In this study, we developed a superior 15 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) with a current spreading layer (CSL) implanted with nitrogen ions. This MOSFET was developed for high-frequency applications. The CSL and junction field-effect transistor (JFET) regions were optimized using device simulations to reduce reverse transfer capacitance without increasing on-resistance. A SiC MOSFET with a CSL and a die with a size of 5 mm × 5 mm was fabricated. We simultaneously obtained a specific on-resistance of 191 mΩ cm2, a blocking voltage of 15.0 kV, and a reverse transfer capacitance of 0.75 pF for a narrow JFET width of 1.2 μm. In addition, threshold voltage shifts were kept within ±0.1 V for 1000 h at a gate voltage of −15 V and at a temperature of 200 °C.

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Reliability Issues of SiC Power MOSFETs toward High Junction Temperature Operation

Tanimoto¹,

Ohashi²

2009

Silicon Carbide

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Comparisons of Design and Yield for Large-Area 10-kV 4H-SiC DMOSFETs

Cited by 12 publications

References 6 publications

11.72 cm<sup>2</sup> SiC Wafer-Scale Interconnected 1.8 kV / 64 kA PiN Diode

11.72 cm<sup>2</sup> SiC Wafer-Scale Interconnected 1.8 kV / 64 kA PiN Diode

A superior 15 kV SiC MOSFET with current spreading layer for high-frequency applications

Reliability Issues of SiC Power MOSFETs toward High Junction Temperature Operation

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