The effects of oxynitridation and wet oxidation at the interface of SiO2/4H-SiC(0001) and were investigated using both electrical and physical characterization methods. Hall measurements and split capacitance–voltage (C–V) measurements revealed that the difference in field-effect mobility between wet oxide and dry oxynitride interfaces was mainly attributed to the ratio of the mobile electron density to the total induced electron density. The surface states close to the conduction band edge causing a significant trapping of inversion carriers were also evaluated. High-resolution Rutherford backscattering spectroscopy (HR-RBS) analysis and high-resolution elastic recoil detection analysis (HR-ERDA) were employed to show the nanometer-scale compositional profile of the SiC-MOS interfaces for the first time. These analyses, together with cathode luminescence (CL) spectroscopy and transmission electron microscopy (TEM), suggested that the deviations of stoichiometry and roughness at the interface defined the effects of oxynitridation and wet oxidation at the interface of SiO2/4H-SiC(0001) and .

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

In this paper, we present a newly developed 1200-V-class 4H-SiC implantation-and-epitaxial trench metal–oxide–semiconductor field-effect transistor (IETMOSFET). It uses high-quality p- and n-epitaxial layers for a channel and a trench current spreading layer (TCSL), respectively. It can enhance both channel mobility and bulk mobility for current spreading by avoiding damage and impurity variations caused by ion implantation. The ion implantation and epitaxial techniques developed for existing ion-implantation-and-epitaxial MOSFETs (IEMOSFETs) are herein utilized to protect the trench bottom and a relatively low-doped epitaxial channel layer with high mobility. By optimizing the geometry of p-base regions under a gate trench structure, we obtain a low specific on-resistance (R ON A) of 1.8 mΩ cm2 with a breakdown voltage (BVDSS) above 1200 V.

In this study, 4H–SiC inversion layers were experimentally evaluated by Hall and split C–V measurements, and scattering mechanisms related to gate oxide nitridation were analyzed. Three typical samples with different crystal plane directions and gate oxidation conditions were prepared, and their total trap density and Hall mobility were compared. Based on the temperature dependence of the Hall mobility, we found that scattering mechanisms differed for each sample. The sample C-face oxynitride which had a high nitrogen density at the metal–oxide–semiconductor (MOS) interface, showed a similar temperature dependency to that of ionized impurity scattering. This result suggests that high-density nitrogen acts as donors that supply free carriers and cause ionized impurity scattering, just like in a bulk crystal. In addition, the sample C-face wet has lowest influence of the Coulomb scattering because of the lowest temperature dependence of Hall mobility and the lowest total trap density.

In this study, we developed a superior 15 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) with a current spreading layer (CSL) implanted with nitrogen ions. This MOSFET was developed for high-frequency applications. The CSL and junction field-effect transistor (JFET) regions were optimized using device simulations to reduce reverse transfer capacitance without increasing on-resistance. A SiC MOSFET with a CSL and a die with a size of 5 mm × 5 mm was fabricated. We simultaneously obtained a specific on-resistance of 191 mΩ cm2, a blocking voltage of 15.0 kV, and a reverse transfer capacitance of 0.75 pF for a narrow JFET width of 1.2 μm. In addition, threshold voltage shifts were kept within ±0.1 V for 1000 h at a gate voltage of −15 V and at a temperature of 200 °C.