Comparison of Two Pole-Zero Cancellation Circuits for Fast Charge Sensitive Amplifier in CMOS Technology

Abstract

The problem of charge sensitive amplifier and pole-zero cancellation circuit designed in CMOS technology for high rates of input pulses is considered. The continuously sensitive charge amplifier uses a MOS transistor biased in triode region to discharge the integration capacitance. Low noise requirements of the front-end electronics place the feedback CSA resistance in hundreds of the Megaohm range. However the high counting rate of input pulses generates a DC voltage shift at the CSA output which could degrade the circuit performance. We analyze two circuit architectures for biasing transistors in feedback of CSA and PZC circuit taking into account the pile-up effects in the signal processing chain.

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“…The preamplifier is generally an opamp with a feedback capacitor designed to integrate current from the detector. To avoid CSP saturation, a feedback reset network (Figure 1) is implemented to discharge the feedback capacitor after each radiation event 18,21,22 . For this purpose, several configurations have been proposed in the literature.…”

“…To avoid CSP saturation, a feedback reset network (Figure 1) is implemented to discharge the feedback capacitor after each radiation event. 18,21,22 For this purpose, several configurations have been proposed in the literature.…”