A baseline restorer for charge-sensitive amplifiers in a 500-nm CMOS process

A PVT power immune compact 65 nm CMOS CSP design with a leakage current compensation feedback for CdZnTe/CdTe sensors dedicated to PET applications

“…For low cost demand and large‐scale integration purpose, the CSP should occupy the smallest possible chip area. In most popular research papers, readout integrated circuits (ROICs) for nuclear instrumentation commonly use technology scale greater than 0.13 μm 25 . However, several researches exploring the performance of sub‐100 nm CMOS FEEs have recently been published 27,28 .…”

“…This has the advantage of compensating the leakage current provided by the photon sensors. [23][24][25][26][27][28] The restoration system proposed by Abusleme et al 25 uses a continuous direct-current (DC) feedback network based on active components. In particular, unlike the Krummenacher network, it is based on the transconductance of the PMOS differential pair biased by an N type metal-oxide semiconductor (NMOS) current mirror.…”

“…In most popular research papers, readout integrated circuits (ROICs) for nuclear instrumentation commonly use technology scale greater than 0.13 μm. 25 However, several researches exploring the performance of sub-100 nm CMOS FEEs have recently been published. 27,28 In Manghisoni et al, 28 65 nm nodes appear to be robust, power efficient, and good manufacturing cost.…”

“…The front‐end ASIC proposed by Ratti et al 23 uses a Krummenacher feedback network for continuous restoration of the integration capacitor. This has the advantage of compensating the leakage current provided by the photon sensors 23–28 . The restoration system proposed by Abusleme et al 25 uses a continuous direct‐current (DC) feedback network based on active components.…”