2012
DOI: 10.1063/1.3689766
|View full text |Cite
|
Sign up to set email alerts
|

Comparison of thermal and atomic-layer-deposited oxides on 4H-SiC after post-oxidation-annealing in nitric oxide

Abstract: The electrical properties of thermally grown and atomic-layer-deposition (ALD) oxides, followed by nitridation treatment, on 4H-SiC substrate were compared. The nitridation treatment was performed with post oxidation annealing in NO atmosphere (NO POA). The best electrical characteristics of the thermally grown and ALD oxides were observed at 120 and 180 min NO POA, respectively. The NO POA treated ALD oxide showed extremely low interface trap density (Dit), less than 1011 eV−1 cm−1. A metal-oxide-semiconducto… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

1
14
0

Year Published

2013
2013
2021
2021

Publication Types

Select...
8

Relationship

0
8

Authors

Journals

citations
Cited by 23 publications
(15 citation statements)
references
References 27 publications
1
14
0
Order By: Relevance
“…To avoid the defects created during high-temperature thermal oxidation, high-quality deposited dielectrics have attracted more research interest [8]- [10]. With the deposited dielectrics, substrate consumption and the amount of carbon released from the substrate can be minimized, and thus the defects associated with thermal oxidation can be greatly reduced.…”
Section: Introductionmentioning
confidence: 99%
“…To avoid the defects created during high-temperature thermal oxidation, high-quality deposited dielectrics have attracted more research interest [8]- [10]. With the deposited dielectrics, substrate consumption and the amount of carbon released from the substrate can be minimized, and thus the defects associated with thermal oxidation can be greatly reduced.…”
Section: Introductionmentioning
confidence: 99%
“…It is known that the electronic structure of the interface fabricated by the thermal oxidation shows different characteristics from that formed by the oxide deposition. 8 The interface stress causes this difference in the electronic structure during the thermal oxidation.…”
mentioning
confidence: 99%
“…It is concluded that the interface stress due to the lattice constant mismatch plays an important role in the removal of C. The SiO 2 layers above the SiC substrate significantly affects the formation process of the interfaces during the thermal oxidation, which is relevant to the characteristic electronic property of the interface fabricated by the thermal oxidation. 8 The first-principles calculations are performed within the framework of density functional theory 9 using the realspace finite-difference approach, [10][11][12][13][14] which provides us with the ground-state atomic and electronic structures using a time-saving double-grid technique. [12][13][14][15] In addition, the realspace finite-difference method enables us to execute the large-scale calculation using massively parallel computers, a)…”
mentioning
confidence: 99%
“…Therefore, the calculated trap density at E c À E t E0.2 eV is 1.3 Á 10 12 cm À 2 eV À 1 . The total density of interface states between 0.2 and 0.6 eV below E c was calculated from the area under the D it vs (E c À E t ) plot in this range, and we have achieved D tot as low as 2.1 Á 10 11 cm À 2 , this value being of the same order of magnitude as those obtained for structures subjected to different post-oxidation treatments dedicated for reduction of the interface states [38]. If the shallow states are included, D tot gets a value of 2.43 Á 10 12 cm À 2 .…”
Section: Sic-based Mos Capacitormentioning
confidence: 99%