Comparison of techniques for bonding VCSELs directly to ICs

Abstract

This paper reports the successful bonding of 8 x 8 and 4 x 4 VCSEL arrays to Si CMOS and GaAs MESFET integrated circuits and to GaAs substrates. Three different bonding techniques are demonstrated and their electrical, optical and lmechanical characteristics are compared. All three techniques remove the substrate from the VCSEL wafer, leaving individual VCSELS bonded directly to locations within the integrated circuit. L IntroductionVCSEL based smart pixel arrays are very desirable for parallel optoelectronic processing and board to board interconnection since they can overcome the electrical interconnect bandwidth bottleneck. The. integration of VCSELS with foundry fabricated integrated circuits is the key technology required to fabricate the smart pixels. For large arrays, the VCSELS need to be bonded directly to the pixels. This has the advantage of low parasitic capacitance, better optical alignment and higher scalability.' There have been a number of previous reports of techniques for bonding VCSEIJ to integrated circuits and other substrates. Pu et al. were the first to report the bonding of an array of VCSELS directly to a foundry fabricated integrated circuits [ 1]. The 8 x 8 array was bonded using a co-planar flip chip bonding process. More recently, Krishnamoorthy et al. reported bonding a 2 x 10 array of 970nm VCSELS to a CM(3S chip [2]. This was also a co-planar bonding process, however the substrate was not removed and the VCSELS emitted through the GaAs substrate. Both of these co-planar techniques were based on previous work on the bonding of SEED arrays [3,4]. Matsuo et al. [5] bonded a VCSEL wafer to a silicon substrate with poiyimide, removed the VCSEL substrate and processed the wafer in to individual VCSELS. Maracas and coworker [(5,7] used a probe transfer technique to place individual VCSELS on a CMOS chip and Smith and coworkers [8] used a fluidic self-alignment technique. These earlier reports showed that VCSELS were robust and could be transferred to another substrate without significant change in electrical/optical characteristics. McLaren et al. [9] reported the thermosonic bonding of an 8 x 8 array to a fused quartz substrate which enabled the VCSEL output to be viewed through the transparent quartz. 90pm square bonding pads on a 250pm pitch were used and the substrate was not removed. This paper reports three techniques for bonding arrays of individual VCSELS to integrated circuits. The optical and electrical measurements of these bonded structures are measured and results compared with each other and those reported by other research groups. II. General Fabrication ConsiderationsDesigning a process for bonding VCSELS directly to locations embedded in an integrated circuit requires making several fundamental fabrication decisions, such as 1) whether or not to remove the VCSEL substrate, 2) the method of current confinement in the VCSELS, 3) the wafer design and 4) the general bonding concept. These design decisions should be based on the specifications for speed of operation...

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