Comparing 32nm full adder TMR and DTMR architectures

Ulloa, Giane; Lucena, Vinicius; Meinhardt, Cristina

doi:10.1109/icecs.2017.8292029

Cited by 2 publications

(1 citation statement)

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“…Many forms of TMR have been presented in recent decades, some of them compromising triplication effectiveness for power consumption or area. The most complete form of TMR, and the one which is addressed in this paper, is full TMR [13] where both the flip-flops, clock-tree and combinational logic are triplicated ( [14,15]) as is shown in Figure 1. This method is the most reliable but also uses the highest number of resources and power.…”

Section: Introductionmentioning

confidence: 99%

Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

2019

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This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

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Section: Introductionmentioning

confidence: 99%

Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

2019

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A Deep Neural Network Accelerator using Residue Arithmetic in a Hybrid Optoelectronic System

Peng

Alkabani

Puri

et al. 2022

J. Emerg. Technol. Comput. Syst.

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The acceleration of Deep Neural Networks (DNNs) has attracted much attention in research. Many critical real-time applications benefit from DNN accelerators but are limited by their compute-intensive nature. This work introduces an accelerator for Convolutional Neural Network (CNN), based on a hybrid optoelectronic computing architecture and residue number system (RNS). The RNS reduces the optical critical path and lowers the power requirements. In addition, the wavelength division multiplexing (WDM) allows high-speed operation at the system level by enabling high-level parallelism. The proposed RNS compute modules use one-hot encoding and thus enable fast switching between the electrical and optical domains. We propose a new architecture that combines residue electrical adders and optical multipliers as the matrix-vector multiplication unit. Moreover, we enhance the implementation of different CNN computational kernels using WDM-enabled RNS based integrated photonics. The area and power efficiency of the proposed accelerator are 0.39 TOPS/s/mm 2 and 3.22 TOPS/s/W, respectively. In terms of computation capability, the proposed chip is 12.7x and 4.02x better than other optical implementation and memristor implementation, respectively. Our experimental evaluation using DNN benchmarks illustrates that our architecture can perform on average more than 72 times faster than GPU under the same power budget.

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Comparing 32nm full adder TMR and DTMR architectures

Cited by 2 publications

References 10 publications

Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

A Deep Neural Network Accelerator using Residue Arithmetic in a Hybrid Optoelectronic System

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