Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

Abstract

Abstract-A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness (T mask ) to the sidewall oxide thickness (T ox ) is T mask /T ox =10/2 nm for the minimum logic delay (τ) while T mask /T ox =5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length (L G ) and the fin width (W fin ) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized T mask /T ox , the propagation delay (τ) decreases with the increasing fin height H fin . It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as H fin increases. In the end, the sensitivity of Δτ/ΔH fin or ΔI ON '/ΔH fin decreases as L G /W fin is scaled-down.However, W fin should be carefully designed especially in circuits that are strongly influenced by the selfcapacitance or a physical layout because the scaling of W fin is followed by the increase of the selfcapacitance portion in the total load capacitance.

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