Comparative analysis of latches and flip-flops for high-performance systems

An Energy-Efficient Differential Flip-Flop for Deeply Pipelined Systems

“…One difference between this study and related work such as [9] is that the flip-flops do not drive a large output load. Thus, we could use small transistors throughout the five circuits.…”

Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic

“…Although the speed, power and power-delay has been analyzed fundamentally extensively for several FF topologies (e.g. [11,12]), there is not much work to optimize Jitter-Power performance. This paper hence derives analytical equations to estimate Jitter, Power and FoM for both DTG and CML-FFs.…”

Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times

“…The setup (hold) time is usually set to the setup (hold) skew where the stable region crosses over into the metastable region. There are different approaches to identify this crossover point [4]. In some approaches, the crossover point is the time where a certain amount of degradation in the CLK-to-Q delay occurs.…”

“…2. According to [4], three regions can be determined for both plots: stable, metastable, and failure regions. The stable region is defined as the region in which the CLK-to-Q delay is independent of the setup or hold skew.…”

“…A common approach to characterize setup time is to examine the setup skew versus CLK-to-Q delay relationship [4], [5] at a fixed hold skew, which is called here the counterpart skew. The process is similar for hold time.…”