Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times

Salman, Emre; Dasdan, Ali; Taraporevala, F.; Kücükcakar, K.; Friedman, Eby G.

doi:10.1109/isqed.2006.100

Cited by 20 publications

(17 citation statements)

References 8 publications

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“…3 and 4 imply that STAs should take into account the interdependent relation between setup skew, hold skew, and clk-to-Q delay in their ip-op timing model, if we really want to avoid unnecessary late-stage ECO (engineering change order) or high cost design change before timing sign-off due to inaccurate analysis of the timing behavior of circuits. Several works analyzed the inter-dependent relation of setup time and hold time and clk-to-Q delay, and used the time relation in their STAs [4][5][6][7][8][9][10]12]. Rao and Howick [4] rstly claried the fact that the setup and hold times have inter-dependent relation.…”

Section: Figmentioning

confidence: 99%

“…They employed Euler-Newton curve tracing method to characterize the inter-dependent setup and hold time contours. Salman et al [7,9] enhanced the accuracy of STA by reecting the inter-dependent relation of setup and hold times, and clkto-Q delay all together, which is commonly called 'exible' timing model in the literature. In their STA, they selected several representative pairs of setup and hold times and stored them in cell library.…”

Section: Figmentioning

confidence: 99%

“…To overcome the inaccuracy of STAs in Fig. 5(a), The STAs in [7][8][9][10] utilized multiple pairs of t S0 and t H0 values for the given value of t Q as indicated in Fig. 5(b), in which the values of t S0 and t H0 at f j can be 25, and 45 as well as 40 and 40, respectively.…”

Section: Motivational Examplesmentioning

confidence: 99%

See 2 more Smart Citations

Post-Silicon Tuning Based on Flexible Flip-Flop Timing

Seo¹,

Heo²,

Kim³

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of ip-ops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate exible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period (T clk ) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of T clk , respectively.

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Section: Figmentioning

confidence: 99%

Section: Figmentioning

confidence: 99%

See 1 more Smart Citation

Post-Silicon Tuning Based on Flexible Flip-Flop Timing

Seo¹,

Heo²,

Kim³

2016

JSTS:Journal of Semiconductor Technology and Science

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“…In [15] a methodology for interdependent setup and hold time characterization of sequential circuits has been presented. However once again this aims at reducing pessimism in Static Timing Analysis without taking into account PV effects on silicon.…”

Section: State Of the Artmentioning

confidence: 99%

Analysis of setup and hold margins inside silicon for advanced technology nodes

Arora

Patel

Shahabuddin

et al. 2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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This paper presents a design and methodology for accurate characterization of setup and hold margins in silicon while taking into account effects of Process Variations (PV). The test circuit provides deeper insights into sources of extra timing margins available on silicon. This in turn, enables accurate guard banding by preventing optimism and reducing unnecessary pessimism in the timing margins provided during sign-off. Our design has been used for the development of the 28nm Fully Depleted Silicon On Insulator (FDSOI) node and associated relevant results and analysis have been provided.

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“…As devices shrink, clock speeds become ever faster, and design margins become increasingly squeezed in high-speed digital systems, it becomes important to determine these quantities with the highest possible accuracy to ensure that timing analysis makes neither unduly optimistic nor pessimistic predictions [2], [4]. Optimism in setup/hold times can cause failure of the fabricated circuits, while pessimism leads to inferior performance.…”

Section: Introductionmentioning

confidence: 99%

Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times

Srivastava

Roychowdhury

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(τ) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for accurate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C 2 MOS latch/register structures, obtaining speedups of 4-10× over the current standard of binary search.

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Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times

Cited by 20 publications

References 8 publications

Post-Silicon Tuning Based on Flexible Flip-Flop Timing

Post-Silicon Tuning Based on Flexible Flip-Flop Timing

Analysis of setup and hold margins inside silicon for advanced technology nodes

Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times

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