Abstract-Injection locking analysis based on classical Adler's equation is limited to LC oscillators as it is dependent on quality factor. In this paper, we present the Generalized Adler's equation applicable for injection locking analysis on oscillators independent of the circuit topology. The equation is obtained by averaging the PPV phase macromodel. The procedure is considerably simple and handy to determine the locking range for arbitrary shape small AC injection signal. Analytical equations for injection locking dynamics are formulated using the Generalized Adler's equation and validated with the PPV simulations.

Abstract-Sub-harmonic injection locking (SHIL) is an interesting phenomenon in nonlinear oscillators that is useful in RF applications, e.g., for frequency division. Existing techniques for analysis and design of SHIL are limited to a few specific circuit topologies. We present a general technique for analysing SHIL that applies uniformly to any kind of oscillator, is highly predictive, and offers novel insights into fundamental properties of SHIL that are useful for design. We demonstrate the power of the technique by applying it to ring and LC oscillators and predicting the presence or absence of SHIL, the number of distinct locks and their stability properties, lock range, etc.. We present comparisons with SPICElevel simulations to validate our method's predictions.is a nonlinear phenomenon in which a self-sustaining oscillator's phase becomes precisely locked (i.e., entrained or synchronized) to that of an externally applied signal. The phenomenon, together with the related effect of injection pulling, has often been regarded as an unwanted disturbance, causing, among other things, malfunction in serial clock/data recovery, increased timing jitter and clock skew, increased BER in communications, etc.. Over the years, however, IL has also been put to good use in electronics -e.g., for quadrature signal generation [4]; for microwave generators in laser optics [5]; for fast, low-power frequency dividers [6]; and in PLLs [7] and wireless sensor networks [8]. Moreover, IL is an important enabling mechanism in biology (e.g., [9], [10]). When an oscillator locks to an external signal whose frequency is close to the oscillator's natural frequency, the phenomenon is termed fundamental harmonic IL. It is also possible, however, for oscillators to phase-lock at a frequency that is an exact integral sub-multiple of the frequency of the externally applied signal; this is termed subharmonic IL (or SHIL, described further in Sec. II-B) and is useful in frequency division applications [6], [7]. Design of circuits exploiting SHIL has tended to rely predominantly on trial-and-error based methodologies, using brute-force transient simulations to assess impact on SHIL-based circuit function. Existing analyses of fundamental and sub-harmonic IL (e.g., [11], [2], [12]) have been limited to very specific circuit topologies (e.g., LC oscillators), while more general analyses [13], that apply to any kind of oscillator, do not consider SHIL. The work of Daryoush et. al. [14] presented a computationally complicated method limited to negative feedback oscillators, and provided no insights about multiple lock states for SHIL. To our knowledge, there is no general analysis or theory that provides the correct design intuition and predictive power for SHIL and related phenomena. In this paper, we develop and validate a general method for analysing and understanding sub-harmonic injection locking. The method applies to any self-sustaining, amplitude-stable oscillator, not only from electronics but also from other domains such as biology. ...

Interdependent characterization of latch setup/hold times is a core component of techniques for pessimism reduction via Setup/Hold Interdependence Aware Static Timing Analysis (SHIA-STA) [1], [2]. We present an efficient and novel method for such characterization, by formulating the interdependent setup-hold time problem as an underdetermined nonlinear equation h(τ s , τ h) = 0, which we derive from the latch's state-transition function. We solve this equation numerically using a Moore-Penrose Newton method. Further, we use null-space information from the Newton's Jacobian matrix to efficiently find constant-clock-to-Q contours (in the setup/hold time plane), via an Euler-Newton curve tracing procedure. We validate the method on TSPC and C 2 MOS registers, obtaining speedups of more than 20× over prior approaches while achieving superior accuracy. This speedup increases linearly with the precision with which curve tracing is desired. In view of the importance and large computational expense of latch characterization in industry today, the new technique represents a significant enabling technology for dramatically speeding up industrial timing closure flows.

Abstract-We describe ModSpec, a MATLAB/Octave based specification format suitable for modelling devices across a wide variety of application domains, including circuits, optics, fluidics and biology. The ModSpec format and associated API are centered around describing the nonlinear differential equations at the core of any device model. The format is open, general and easy to use, and is supported by toolchains that translate and automatically differentiate models, set up equations for systems of interacting devices, and provide simulation facilities. We illustrate the use of ModSpec for modelling semiconductor, photovoltaic, fluidic and neuronal devices and systems.

Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(τ) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for accurate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C 2 MOS latch/register structures, obtaining speedups of 4-10× over the current standard of binary search.