Compact Models of Voltage Drops in Power Delivery Network for TSV-Based Three-Dimensional Integration

He, Huanyu; Lu, Jian‐Qiang

doi:10.1109/led.2013.2238214

Cited by 14 publications

(7 citation statements)

References 6 publications

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“…The overall voltage drops are basically dominated by the vertical voltage drops, which in this case are mainly caused by voltage drops on the TSVs and micro-bumps. With the assumption of uniform current consumption, the vertical voltage drop follows a quadratic relation with the number of chips and is inversely proportional to the number of TSVs [11]. The vertical voltage drop…”

Section: Voltage Drop In 3d Power Networkmentioning

confidence: 99%

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Power delivery modeling for 3D systems with non-uniform TSV distribution

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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This paper reports on power delivery modeling for 3D systems where through-silicon vias (TSVs) are not uniformly distributed, but are arranged at the peripheries of circuit blocks and die edges. The voltage drop (IR) and di/dt noise on the power delivery are modeled and compared with those given by uniformly distributed TSVs. The impact of TSV density and circuit block size, and their tradeoffs are evaluated.

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Section: Voltage Drop In 3d Power Networkmentioning

confidence: 99%

“…enough number of TSVs [11]. Here I is the total current consumed by one chip, and 69 m   is determined by the grid wire parasitics, dimensions and configuration.…”

Section: Voltage Drop In 3d Power Networkmentioning

confidence: 99%

Power delivery modeling for 3D systems with non-uniform TSV distribution

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…One of the interesting phenomena occurring in this type of cooling systems, and yet to be studied, is the interaction between the electric, magnetic, thermal and pressure fields involved. Savidis et al [7], He and Lu [8], Xie and Swaminathan [9], He et al [10] and Xie et al [11] investigated voltage drops in power delivery network for TSV-based 3D integration packages. It is well understood that electric fields and magnetic fields can influence the flow-field and consequently the heat transfer [12].…”

Section: Introductionmentioning

confidence: 99%

Effect of cooling fluids on high frequency electric and magnetic fields in microelectronic systems with integrated TSVs

Abdoli

Reddy

Dulikravich

et al. 2017

Microelectronics Journal

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A B S T R A C TA fully 3D conjugate numerical analysis was performed to reveal the effects of air, R134a refrigerant and water on electromagnetic fields of electronic cooling designs made of arrays of micro pin-fins with integrated Through-Silicon-Vias (TSVs). The integrated TSV cooling configuration included 8 cylindrical TSVs with 150 µm diameter each and 200 µm height. The external dimensions of the silicon substrate were 900×700×280 µm. Each TSV encapsulated four equally spaced copper vias each having a diameter of 40 µm. The impacts of the presence of the stationary cooling fluids without heat transfer on TSVs electric and magnetic fields were examined for five different frequencies; 100 MHz, 500 MHz, 1 GHz, 5 GHz and 10 GHz. Then, separately, the effects of moving cooling water with temperature-dependent physical properties were studied while exposing the cooled micro pin-fin array to a uniform heat flux of 500 W cm −2 . For the case of stagnant and moving cooling fluids it was found that water influences the electric field twice as much as either R134a or air and that this influence decreases only negligibly with the increase in frequency of the electric current passing through the TSVs. The influence of the presence of the stagnant and moving cooling fluids on the magnetic field is orders of magnitude smaller and reduces rapidly with the increased frequency.

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“…The resistance of the TSV and on-chip PDN resulted in a significant impact on the voltage drop in a 3D IC. [12] proposed compact models of the IR drop in a 3D IC PDN. They claimed that the voltage drop has a quadratic dependency on the number of chips in a stack.…”

Section: Introductionmentioning

confidence: 99%

Novel adaptive power gating strategy of TSV-based multi-layer 3D IC

Kim

Kang

Han

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

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Among power dissipation components, the leakage power has become more dominant with each successive technology node. A power gating technique has been widely used to reduce the standby leakage energy. In this work, we investigate the power gating strategy of TSV-based 3D IC stacking structures. Power gating control is becoming more complicated as more dies are stacked. We combine the on-chip PDN and TSV in a multilayered 3D IC for a power gating analysis of the static and dynamic voltage drops and in-rush current. Then, we propose a novel power gating strategy that optimizes the inrush current profile, subject to the voltage-drop constraints. Our power gating strategy provides a minimal wake-up latency such that the voltage noise safety margins are not violated. In addition, the layer dependency of the 3D IC on the power gating in terms of the wake-up time reduction is analyzed. We achieve an average wake-up time reduction of 28% for all cases with our adaptive power gating method that exploits location (or layer) information of the aggressors in a 3D IC.

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Compact Models of Voltage Drops in Power Delivery Network for TSV-Based Three-Dimensional Integration

Cited by 14 publications

References 6 publications

Power delivery modeling for 3D systems with non-uniform TSV distribution

Power delivery modeling for 3D systems with non-uniform TSV distribution

Effect of cooling fluids on high frequency electric and magnetic fields in microelectronic systems with integrated TSVs

Novel adaptive power gating strategy of TSV-based multi-layer 3D IC

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