Power delivery modeling for 3D systems with non-uniform TSV distribution

He, Huanyu; Xu, Zheng; Gu, Xiaoxiong; Lü, Jian–Qiang

doi:10.1109/ectc.2013.6575713

Cited by 7 publications

(3 citation statements)

References 8 publications

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“…We compared the proposed algorithm with the conventional algorithms in order to verify the superiority of the proposed algorithm in minimising the number of power TSVs and bumps while satisfying the IR drop constraint without an increase in the area. In [15], a 3D power delivery network modelling is proposed with a peripheral TSV arrangement and the power TSVs are placed at the four‐sided boundary of the power delivery network. For the absolute comparison with our proposed algorithm, as controlling interval between the inserted power TSVs to search the minimised number of power TSVs to satisfy IR drop constraint, the number of power TSVs is controlled.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…In some of the recent studies of 3D power delivery network, initial power bumps are placed in a regular configuration with a fixed mesh structure, and the number and location of power TSVs are optimised to satisfy IR drop constraint in 3D ICs [13, 14]. In [15], the authors proposed power delivery network modelling with peripheral TSV arrangement for 3D IC. However, in these studies, the number of power bumps is greater than necessary because of the regular placement of power bumps while the room for clock bumps and signal bumps is limited.…”

Section: Introductionmentioning

confidence: 99%

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Power‐aware floorplanning‐based power through‐silicon‐via technology and bump minimisation for three‐dimensional power delivery network

Jang¹,

Kim²,

Chong³

2014

IET Computers & Digital Techniques

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Three-dimensional (3D) integrated circuits, which use a vertically stacked design of 2D planar chips in a 3D arrangement using through-silicon-via (TSV) technology have been developed to minimise chip footprint, enable higher integration density, decrease power consumption and reduce fabrication cost. Floorplanning without considering power can increase the number of power TSVs and bumps needed to solve IR drop constraint in 3D power delivery network. In this study, the authors propose a methodology for minimising the power TSVs and bumps based on power-aware floorplanning using specific power patterns to solve IR drop constraint on the 3D power delivery network. The authors' methodology moves high power-consuming blocks to the dedicated pattern area which is able to minimise the number of power TSVs and bumps while solving the IR drop constraint. The simulation results show that the proposed method can reduce the total number of power TSVs and bumps by 13.7 and 12.2%, respectively, after power-aware floorplanning while solving the IR drop constraint.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Power‐aware floorplanning‐based power through‐silicon‐via technology and bump minimisation for three‐dimensional power delivery network

Jang¹,

Kim²,

Chong³

2014

IET Computers & Digital Techniques

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“…One of the interesting phenomena occurring in this type of cooling systems, and yet to be studied, is the interaction between the electric, magnetic, thermal and pressure fields involved. Savidis et al [7], He and Lu [8], Xie and Swaminathan [9], He et al [10] and Xie et al [11] investigated voltage drops in power delivery network for TSV-based 3D integration packages. It is well understood that electric fields and magnetic fields can influence the flow-field and consequently the heat transfer [12].…”

Section: Introductionmentioning

confidence: 99%

Effect of cooling fluids on high frequency electric and magnetic fields in microelectronic systems with integrated TSVs

Abdoli

Reddy

Dulikravich

et al. 2017

Microelectronics Journal

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A B S T R A C TA fully 3D conjugate numerical analysis was performed to reveal the effects of air, R134a refrigerant and water on electromagnetic fields of electronic cooling designs made of arrays of micro pin-fins with integrated Through-Silicon-Vias (TSVs). The integrated TSV cooling configuration included 8 cylindrical TSVs with 150 µm diameter each and 200 µm height. The external dimensions of the silicon substrate were 900×700×280 µm. Each TSV encapsulated four equally spaced copper vias each having a diameter of 40 µm. The impacts of the presence of the stationary cooling fluids without heat transfer on TSVs electric and magnetic fields were examined for five different frequencies; 100 MHz, 500 MHz, 1 GHz, 5 GHz and 10 GHz. Then, separately, the effects of moving cooling water with temperature-dependent physical properties were studied while exposing the cooled micro pin-fin array to a uniform heat flux of 500 W cm −2 . For the case of stagnant and moving cooling fluids it was found that water influences the electric field twice as much as either R134a or air and that this influence decreases only negligibly with the increase in frequency of the electric current passing through the TSVs. The influence of the presence of the stagnant and moving cooling fluids on the magnetic field is orders of magnitude smaller and reduces rapidly with the increased frequency.

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Analysis of TSV geometric parameter impact on switching noise in 3D power distribution network

2014

25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014)

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Power delivery modeling for 3D systems with non-uniform TSV distribution

Cited by 7 publications

References 8 publications

Power‐aware floorplanning‐based power through‐silicon‐via technology and bump minimisation for three‐dimensional power delivery network

Power‐aware floorplanning‐based power through‐silicon‐via technology and bump minimisation for three‐dimensional power delivery network

Effect of cooling fluids on high frequency electric and magnetic fields in microelectronic systems with integrated TSVs

Analysis of TSV geometric parameter impact on switching noise in 3D power distribution network

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