Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Wang, Wenping; Reddy, V.; Krishnan, A.T.; Vattikonda, Rakesh; Krishnan, S.; Cao, Yu

doi:10.1109/tdmr.2007.910130

Cited by 271 publications

(14 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The modeling of the NBTI by the use of a gate voltage source has been proposed and implemented for Si-MOSFETs. 20 Fig . 4 shows the effect of the correlation length and the position of impurities on the transmission probability.…”

Section: Resultsmentioning

confidence: 99%

On the role of disorder on graphene and graphene nanoribbon-based vertical tunneling transistors

Ghobadi

Pourfath

2014

Journal of Applied Physics

View full text Add to dashboard Cite

In this work, the characteristics of vertical tunneling field-effect transistors based on graphene (VTGFET) and graphene nanoribbon heterostructure (VTGNRFET) in the presence of disorder are theoretically investigated. An statistical analysis based on an atomistic tight-binding model for the electronic bandstructure along with the non-equilibrium Green's function formalism are employed. We study the dependence of the averaged density of states, transmission probability, on- and off-state conductances, on/off conductance ratio, and transfer characteristics on the substrate induced potential fluctuations and vacancies. In addition, the variabilities of the device characteristics due to the presence of disorder are evaluated. It can be inferred from the results that while introducing vacancies cause a relatively modest suppression of the transmission probability, potential fluctuations lead to the significant increase of transmission probability and conductance of the device. Moreover, the results show that the transport properties of VTGFET are more robust against disorder compared to VTGNRFET.

show abstract

Section: Resultsmentioning

confidence: 99%

On the role of disorder on graphene and graphene nanoribbon-based vertical tunneling transistors

Ghobadi

Pourfath

2014

Journal of Applied Physics

View full text Add to dashboard Cite

show abstract

“…Further, Fig. 13(b) shows the 11 stage SiNW FET RO degradation is compared to the planar CMOS [26], we note that NW CMOS has higher degradation due to trapping and large interface state degeneration in gate oxide due to cylindrical structure with respect to planar RO. …”

Section: Impact Of Nbti On Circuit Performancementioning

confidence: 97%

“…SiNW (This work) Planar CMOS [24] FinFET [25] FinFET [25] Inverter delay (a) (This work) 10nm SiNW (This work) Planar CMOS [26] Planar CMOS [26] 11-Stage RO hold, read and write modes [27]. For this, first, we briefly review the HOLD, READ and WRITE operation and sizing of the SRAM transistors.…”

Section: Time (S)mentioning

confidence: 99%

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

Prakash

Beniwal²,

Maheshwaram³

et al. 2017

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

 Abstract-For sub-20nm FinFET and nanowire CMOS devices, NBTI is an important reliability issue, and requires an accurate model to predict device and circuit performance. In this paper, we report well calibrated predictive and scalable compact Verilog-A based compact model, integrated with NBTI model for nanowire (NW) CMOS circuit simulation and design. The stress and recovery NBTI model for Si NW FET is obtained from experimental NW pMOSFETs using range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar MOSFETs. This is attributed to its cylindrical gate structure resulting in enhanced 2-D hydrogen diffusion and stress induced Si/SiO 2 traps. This emphasizes need for evaluating NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, and interface states generation, inverter delay and RO frequency degrades rapidly and saturates in long term 10-year lifetime. Finally, design of SRAM cell employing multi-wire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using appropriate design configuration. This study underscores need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at device and circuit level. Index Terms-CompactModeling, Negative Bias Temperature Instability (NBTI), Stress and Recovery Modeling, Silicon nanowire FET/CMOS, Si NW SRAM.

show abstract

“…It, however, causes reliability and process variations concerns that were previously not so catastrophic in micron-based technologies. The situation becomes alarming for low voltage and power applications [1,2] due to systematic scaling down in oxide thickness, which requires lowering of the maximum tolerable voltage across the transistor terminals to ensure lifetime. As some standardised protocols or ICs are working with higher supply voltages and necessitate connection between these blocks and low-voltage analog blocks, thereby leading to device stress [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Programmable CCCII: reliability analysis and design methodology

Tiwari

Pandey

Paul

et al. 2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

In this study, an effective and efficient approach for reliability analysis is developed to bridge the gap between devicelevel reliability and that at the product level. Continual reduction of device dimensions, gate-oxide and increase in channel doping results in an increased electric field which is introducing most of the reliability concerns. Four most important reliability issues impacting circuit design are hot carrier injection, bias temperature instability, time-dependent dielectric breakdown and self-heating. As the second-generation current controlled conveyor (CCCII) circuit are used to implement oscillator, filter clock and so on, which are working continuously even in sleep mode. So it is important to take care of all the reliability aspects while designing CCCII. There is a challenge in complex design to identify which devices (MOS, resistor and capacitor) are susceptible to degradation and then redesign and mitigate this effect for a robust and reliable design. The objective of this work is to detect reliability issues and design a programmable current conveyor which can work safely for a long duration. The circuit has been designed and simulated using 28 nm CMOS technology model parameters on Cadence Virtuoso/AMS environment (ELDO simulator) using ± 1.8 V supply voltage and results have been verified with post-layout netlist.

show abstract

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Cited by 271 publications

References 25 publications

On the role of disorder on graphene and graphene nanoribbon-based vertical tunneling transistors

On the role of disorder on graphene and graphene nanoribbon-based vertical tunneling transistors

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

Programmable CCCII: reliability analysis and design methodology

Contact Info

Product

Resources

About