Compact model and performance estimation for tunneling nanowire FET

Solomon, P. M.; Frank, D.J.; Koswatta, S. O.

doi:10.1109/drc.2011.5994495

Cited by 25 publications

(10 citation statements)

References 6 publications

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“…7(a) shows that while the V (x) curve of (3) for V gs = V ds = 0.5 V is consistent with that of Sentaurus simulations [21], the curve for V gs = 0.5 V and V ds = 0.1 V is far-off. This is because of the de-biasing effect of inversion charge [7], [9], [14] when the Fermi level of Fig. 9.…”

Section: Short-channel Tfet I -V Characteristicsmentioning

confidence: 99%

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Short-Channel Effects in Tunnel FETs

Min

Taur

2015

IEEE Trans. Electron Devices

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This paper investigates short-channel effects (SCEs) in double-gate tunnel FETs (TFETs) using an analytic model that includes depletion in the source. It is shown that the drain bias has a significant effect on the potential profile at the source when the channel length is reduced to below twice the scale length. The OFF-state current becomes a strong function of channel length. The subthreshold current slope is also degraded in short-channel TFETs to the extent that there is no region of <60 mV/decade below a minimum channel length. The SCE also manifests itself in the finite-output conductance in the saturation region-a Drain-Induced Barrier Lowering-like effect in conventional MOSFETs.Index Terms-Band-to-band tunneling, short-channel effect (SCE), tunnel FET (TFET).Jianzhi Wu (S'14) received the B.S. degree in optical information science and technology from Southeast University, Nanjing, China, in 2010, and the M.S.

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Section: Short-channel Tfet I -V Characteristicsmentioning

confidence: 99%

“…Most TFET models in the literature dealt with long-channel devices [2]- [12]. In [7], an exponential barrier based on the scale length theory was employed in a compact model. However, no effect of drain bias was considered.…”

Section: Introductionmentioning

confidence: 99%

Short-Channel Effects in Tunnel FETs

Min

Taur

2015

IEEE Trans. Electron Devices

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“…[4][5][6][7][8][9] employ a semianalytical solution of Poisson's equation in the channel region to model the channel charge [4] or to obtain the current-voltage characteristics [5][6][7][8][9]. These reports focus on particular TFET gate configurations, single-gate (SG) [5][6][7], double-gate (DG) [4,8,9,11], or gate-all-around [10], or on specific aspects of the transport, such as the output characteristic at small drain biases [12,13]. In most cases, the resulting expressions for the drain current are complex because the aim is to be predictive.…”

Section: Introductionmentioning

confidence: 99%

“…Quite a few compact analytic models for the TFET have been developed [4][5][6][7][8][9][10][11][12][13][14]. Refs.…”

Section: Introductionmentioning

confidence: 99%

Universal analytic model for tunnel FET circuit simulation

Esseni

Seabaugh

2015

Solid-State Electronics

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“…9, the PROCEED predictions are in much better agreement with the comprehensive optimized results from the register-transfer level (RTL) compiler compared with Model [4], which is frequently used for device evaluation [2], [3]. The operating range for comparison is chosen by the synthesis results with the commercial library using one V dd and V t .…”

Section: A Framework Evaluationmentioning

confidence: 99%

PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices

Wang

Pan

Chui

et al. 2016

IEEE Trans. VLSI Syst.

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Evaluation of novel devices in the context of circuits is crucial to identifying and maximizing their value. We propose a new framework, Pareto optimization-based circuit-level evaluator for emerging device (PROCEED), that uses comprehensive performance, power, and area metrics for accurate device-circuit coevaluation through optimization of digital circuit benchmarks. The PROCEED assesses technology suitability over a wide operating region (megahertz to gigahertz) by leveraging available circuit knobs (threshold voltage assignment, power management, sizing, and so on). It improves the benchmark accuracy by 3× to 115× compared with the existing methods while offering orders of magnitude improvements in runtime over full physical design implementation flows. To illustrate the PROCEED's capabilities, we deploy it to assess emerging technologies, including novel tunneling field-effect transistors, compared with conventional silicon CMOS. As a further illustration, we extend PROCEED to evaluate future heterogeneous integration of varied devices onto the same silicon substrate. Index Terms-Circuit-level device evaluation, Pareto optimization, silicon-on-insulator (SOI), simulation-based optimization, tunneling field-effect transistor (TFET).

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Compact model and performance estimation for tunneling nanowire FET

Cited by 25 publications

References 6 publications

Short-Channel Effects in Tunnel FETs

Short-Channel Effects in Tunnel FETs

Universal analytic model for tunnel FET circuit simulation

PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices

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