Compact low-power high-slew-rate buffer for LCD driver applications

Abstract

A very compact, rail-to-rail, low-power, high-speed buffer amplifier for LCD driver applications is proposed. A slew-rate enhancement technique based on a dynamic current bias scheme is adopted, and a high slew-rate is obtained without increasing the quiescent current. The buffer amplifier uses a small number of transistors and enables very small active layout area. The proposed buffer amplifier is suitable for both low-and high-voltage LCD driver applications.Introduction: As liquid-crystal displays (LCDs) approach high resolution, high quality, and physically large panel size, the design of output buffer amplifiers becomes more challenging. More specifically, the buffer amplifier needs to be faster in order to deal with larger load capacitance and resistance and thereby achieve smaller settling time. In addition, hundreds or thousands of output buffer amplifiers are integrated into one driver IC, and the buffer should occupy a small die area and consume small static power. It also should provide a rail-to-rail voltage driving capability so that higher grey levels can be accommodated.To reduce settling time, the slew-rate of the buffer amplifier should be increased, because the slewing time normally dominates the settling time in LCD applications. Several techniques have thus far been used to increase slew-rate without additional static power. Lu [1, 2] used additional comparators to sense the rising/falling edges of the input and then turn on push/pull transistors in the output stage to charge/discharge the output load. Yu and Wu [3] proposed a class B buffer in which a comparator is used in the negative feedback path to eliminate the static current in the output stage. Kim and Cho [4] adopted positive feedback loops to speed up the slew-rate of the proposed buffer when there is a voltage difference in the differential input. Choi et al. [5] developed an adaptive dynamic current biasing scheme to increase slew-rate without increasing the quiescent current. In this Letter we propose a very compact low-power high-speed rail-to-rail buffer amplifier using a slew-rate enhancement technique (SRET) based on the adaptive current biasing scheme [5].

Energy-efficient, fast-settling, modified nested-current-mirror, single-stage-amplifier for high-resolution LCDs in 90-nm CMOS

“…These buffers normally employ closed loop amplifiers to drive a heavy capacitive load around 1-10 nF depending on the size and resolution of the display. Energy efficiency is very important for this LCDs, since they are one of the most power-hungry parts of these iOT devices [136][137][138][139][140][141][142][143][144][145]. As another example, Fig.…”

“…LCD panels are widely used modules in iOT applications. Modern mobile devices, smart phones, modern medical/health-care systems, and modern TVs utilize high performance LCDs, which have a wide range of capacitive loads [135][136][137][138][139][140][141][142][143][144][145][146][147][148][149][150]. As these displays increase their resolution, quality and size, the design of column output buffers becomes more and more challenging [140].…”

“…The LCD column drivers includes data-latches, shift-registers, input-registers, levelshifters, DACs and output-buffers as shown in Fig. 3.6 (a) [135][136][137][138][139][140][141]. DACs and output buffers often determine the speed, resolution, voltage swing, and power dissipation of a column driver [135][136][137][138][139][140][141].…”

Two capacitive-pulling techniques to aid the settling of SC residue amplifier

“…The time spent in slewing is taken away from the linear settling time, and this causes highly non-linear settling error [1]. Alternative slew rate (SR) enhancing approaches include: increasing DC bias current of the OTA which increases the power dissipation; adaptive biasing technique in a class-AB input stage [2], but combining the class-AB operation and rail to rail signal swing in [2] usually requires a complicated biasing circuit to extend the common-mode input range of the buffer, this increases the overall circuit complexity and power consumption; a novel adaptive biasing circuit [3] that senses the voltage difference of input and boosts the tail current by a positive feedback, but only works for single stage OTAs; [4] adopts an auxiliary monitor circuit to adjust the driving current but can hardly operate under a low supply voltage; [5] employs a dynamic bias current for a large output current but only works for single stage OTAs; [6] presents a low-voltage SR enhancement technique used in two-stage OTA which detects input voltage of the OTA and brings an external boost current to the OTA while the OTA is slewing; a charge pump [7], where the on-times of up and down currents are controlled by two comparators, performing rapid change of the OTA bias condition between a low-current mode and a high-current mode during non-overlapping clock periods of the two phase clocks; Modifying the OTA bias requires that the OTA is dimensioned to handle the boosted current, and may cause some internal settling transients. In this paper we present a solution, where the boosting is done outside the OTA, based on prior knowledge of the charge sharing.…”

Dynamic Slew-Rate Control for High Uniformity and Low Power in LCD Driver ICs

“…1(b). In order to alleviate these display defects, the slew rate of the DDI is usually designed to be extremely fast [1,2]. However, a faster slew rate is accompanied by an increase in the power consumption as well as higher radiation of EMI.…”